| Message ID | SEYPR01MB42211B13FF62603E3E18B8DCD7A22@SEYPR01MB4221.apcprd01.prod.exchangelabs.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Daniel Lezcano |
| Headers | show |
| Series | riscv: sophgo: add thermal sensor support for cv180x/sg200x SoCs | expand |
On 2024/7/16 17:42, Haylen Chu wrote: > Add common sensor device Sophgo CV18xx SoCs and thermal zone for > CV1800b SoCs. > > Signed-off-by: Haylen Chu <heylenay@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 30 +++++++++++++++++++++++++ > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 8 +++++++ > 2 files changed, 38 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > index ec9530972ae2..0b5c7bc94b05 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -12,6 +12,34 @@ memory@80000000 { > device_type = "memory"; > reg = <0x80000000 0x4000000>; > }; > + > + thermal-zones { > + soc-thermal { > + polling-delay-passive = <1000>; > + polling-delay = <1000>; > + thermal-sensors = <&soc_temp>; > + > + trips { > + soc_passive: soc-passive { > + temperature = <75000>; > + hysteresis = <5000>; > + type = "passive"; > + }; > + > + soc_hot: soc-hot { > + temperature = <85000>; > + hysteresis = <5000>; > + type = "hot"; > + }; > + > + soc_critical: soc-critical { > + temperature = <100000>; > + hysteresis = <0>; > + type = "critical"; > + }; > + }; > + }; > + }; > }; > > &plic { > @@ -25,3 +53,5 @@ &clint { > &clk { > compatible = "sophgo,cv1800-clk"; > }; > + > + > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > index 891932ae470f..76b02cc279aa 100644 > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > @@ -310,5 +310,13 @@ clint: timer@74000000 { > reg = <0x74000000 0x10000>; > interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > }; > + > + soc_temp: thermal-sensor@30e0000 { Nodes on any bus, thus using unit addresses for children, shall be ordered by unit address in ascending order. See https://docs.kernel.org/devicetree/bindings/dts-coding-style.html. > + compatible = "sophgo,cv1800-thermal"; > + reg = <0x30e0000 0x100>; > + clocks = <&clk CLK_TEMPSEN>; > + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; > + #thermal-sensor-cells = <0>; > + }; > }; > };
On 16/07/2024 11:42, Haylen Chu wrote: > + soc_critical: soc-critical { > + temperature = <100000>; > + hysteresis = <0>; > + type = "critical"; > + }; > + }; > + }; > + }; > }; > > &plic { > @@ -25,3 +53,5 @@ &clint { > &clk { > compatible = "sophgo,cv1800-clk"; > }; > + > + Why? Drop. Best regards, Krzysztof
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index ec9530972ae2..0b5c7bc94b05 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -12,6 +12,34 @@ memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&soc_temp>; + + trips { + soc_passive: soc-passive { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + soc_hot: soc-hot { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + + soc_critical: soc-critical { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; &plic { @@ -25,3 +53,5 @@ &clint { &clk { compatible = "sophgo,cv1800-clk"; }; + + diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 891932ae470f..76b02cc279aa 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -310,5 +310,13 @@ clint: timer@74000000 { reg = <0x74000000 0x10000>; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; }; + + soc_temp: thermal-sensor@30e0000 { + compatible = "sophgo,cv1800-thermal"; + reg = <0x30e0000 0x100>; + clocks = <&clk CLK_TEMPSEN>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <0>; + }; }; };
Add common sensor device Sophgo CV18xx SoCs and thermal zone for CV1800b SoCs. Signed-off-by: Haylen Chu <heylenay@outlook.com> --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 30 +++++++++++++++++++++++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 8 +++++++ 2 files changed, 38 insertions(+)