| Message ID | SG2PR01MB42184CFE2C3D3E210CC6F7DAD7F82@SG2PR01MB4218.apcprd01.prod.exchangelabs.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Daniel Lezcano |
| Headers | show |
| Series | riscv: sophgo: add thermal sensor support for cv180x/sg200x SoCs | expand |
Hi Haylen,
kernel test robot noticed the following build warnings:
[auto build test WARNING on rafael-pm/thermal]
[also build test WARNING on robh/for-next linus/master v6.10-rc2 next-20240606]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Haylen-Chu/dt-bindings-thermal-sophgo-cv180x-thermal-Add-Sophgo-CV180x-thermal/20240604-205916
base: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git thermal
patch link: https://lore.kernel.org/r/SG2PR01MB42184CFE2C3D3E210CC6F7DAD7F82%40SG2PR01MB4218.apcprd01.prod.exchangelabs.com
patch subject: [PATCH v2 2/3] riscv: dts: sophgo: cv18xx: Add sensor device and thermal zone
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project d7d2d4f53fc79b4b58e8d8d08151b577c3699d4a)
dtschema version: 2024.6.dev1+g833054f
reproduce: (https://download.01.org/0day-ci/archive/20240607/202406070442.HO8jNHCo-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406070442.HO8jNHCo-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dtb: thermal-zones: 'soc-thermal-0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/thermal/thermal-zones.yaml#
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index ec9530972ae2..9e669ab35380 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -12,6 +12,34 @@ memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; }; + + thermal-zones { + soc-thermal-0 { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&soc_temp>; + + trips { + soc_passive: soc-passive { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + soc_hot: soc-hot { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + + soc_critical: soc-critical { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; &plic { @@ -25,3 +53,5 @@ &clint { &clk { compatible = "sophgo,cv1800-clk"; }; + + diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 891932ae470f..b165866d4cad 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -310,5 +310,13 @@ clint: timer@74000000 { reg = <0x74000000 0x10000>; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; }; + + soc_temp: thermal-sensor@30e0000 { + compatible = "sophgo,cv180x-thermal"; + reg = <0x30e0000 0x100>; + clocks = <&clk CLK_TEMPSEN>; + clock-names = "clk_tempsen"; + #thermal-sensor-cells = <0>; + }; }; };
Add common sensor device Sophgo CV18xx SoCs and thermal zone for CV1800b SoCs. Signed-off-by: Haylen Chu <heylenay@outlook.com> --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 30 +++++++++++++++++++++++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 8 +++++++ 2 files changed, 38 insertions(+)