diff --git a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml
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+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic i.MX bus frequency device
+
+maintainers:
+  - Leonard Crestez <leonard.crestez@nxp.com>
+
+description: |
+  The i.MX SoC family has multiple buses for which clock frequency (and
+  sometimes voltage) can be adjusted.
+
+  Some of those buses expose register areas mentioned in the memory maps as GPV
+  ("Global Programmers View") but not all. Access to this area might be denied
+  for normal (non-secure) world.
+
+  The buses are based on externally licensed IPs such as ARM NIC-301 and
+  Arteris FlexNOC but DT bindings are specific to the integration of these bus
+  interconnect IPs into imx SOCs.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+        - enum:
+          - fsl,imx8mn-nic
+          - fsl,imx8mm-nic
+          - fsl,imx8mq-nic
+        - const: fsl,imx8m-nic
+      - items:
+        - enum:
+          - fsl,imx8mn-noc
+          - fsl,imx8mm-noc
+          - fsl,imx8mq-noc
+        - const: fsl,imx8m-noc
+      - const: fsl, imx8m-nic
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  operating-points-v2: true
+  opp-table: true
+
+  fsl,ddrc:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+    description:
+      Phandle to DDR Controller.
+
+  '#interconnect-cells':
+    description:
+      If specified then also act as an interconnect provider. Should only be
+      set once per soc on the main noc.
+    const: 1
+
+required:
+  - compatible
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/interconnect/imx8mm.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+noc: interconnect@32700000 {
+        compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
+        reg = <0x32700000 0x100000>;
+        clocks = <&clk IMX8MM_CLK_NOC>;
+        #interconnect-cells = <1>;
+
+        /* Used to make requests for DEV_PM_QOS_MIN_FREQUENCY: */
+        fsl,scalable-node-ids = <IMX8MM_ICN_NOC>,
+                                <IMX8MM_ICN_MIPI>,
+                                <IMX8MM_ICS_DRAM>;
+        fsl,scalable-nodes = <&noc>,
+                             <&pl301_mipi>,
+                             <&ddrc>;
+
+        /* For passive governor: */
+        devfreq = <&ddrc>;
+
+        operating-points-v2 = <&noc_opp_table>;
+        noc_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-133M {
+                        opp-hz = /bits/ 64 <133333333>;
+                };
+                opp-800M {
+                        opp-hz = /bits/ 64 <800000000>;
+                };
+        };
+};
+
+pl301_mipi: interconnect@32500000 {
+        compatible = "fsl,imx8m-nic";
+        reg = <0x32500000 0x100000>;
+        clocks = <&clk IMX8MM_CLK_DISP_AXI>;
+        operating-points-v2 = <&pl301_mipi_opp_table>;
+
+        pl301_mipi_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-200M {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+                opp-500M {
+                        opp-hz = /bits/ 64 <500000000>;
+                };
+        };
+};
+
+ddrc: memory-controller@3d400000 {
+        compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
+        reg = <0x3d400000 0x400000>;
+        glock-names = "core", "pll", "alt", "apb";
+        clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
+                 <&clk IMX8MM_DRAM_PLL>,
+                 <&clk IMX8MM_CLK_DRAM_ALT>,
+                 <&clk IMX8MM_CLK_DRAM_APB>;
+        /* For ondemand governor: */
+        devfreq-events = <&ddr_pmu>;
+};
+
+ddr_pmu: ddr-pmu@3d800000 {
+        compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
+        reg = <0x3d800000 0x400000>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+};
