From patchwork Wed Mar 1 05:27:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Len Brown X-Patchwork-Id: 9597719 X-Patchwork-Delegate: rjw@sisk.pl Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 46ADC60414 for ; Wed, 1 Mar 2017 07:15:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 38472284F4 for ; Wed, 1 Mar 2017 07:15:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2AD45284F9; Wed, 1 Mar 2017 07:15:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE26C284F4 for ; Wed, 1 Mar 2017 07:14:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751435AbdCAHOX (ORCPT ); Wed, 1 Mar 2017 02:14:23 -0500 Received: from mail-qk0-f193.google.com ([209.85.220.193]:34669 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751499AbdCAHOV (ORCPT ); Wed, 1 Mar 2017 02:14:21 -0500 Received: by mail-qk0-f193.google.com with SMTP id s186so8621065qkb.1; Tue, 28 Feb 2017 23:13:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:reply-to:organization; bh=OjqhXtIu4tfuUuqmTzA0h3T7qRniA71xVyU4J5hMdTE=; b=kmoOVyU5JPK3R/1fYZrF4EEAQNKVg2BrOXuWqhcSQTNtqaUHwZxtWovOV9j4adPyzT IGx5LtGQ+MDSJ/46TkpeG4WJbH54ZCV+gp0jqjm/FgmcNu8qXvK/YoT0pcT15+4xuQpd 2ygCNKvIKV8djWhim484UOW+mt+bzPmesD2Yb3G1e/z0Eof1fU3We6GPgMYQ0pV1WMEu Y167p5+c5My+4swh0uBsk8ZwGMwrGEf8++hY8M1ZAZAj9JFqdng/3NljGshh9NAnoCrZ 88Lo2bjmaWRmzpuA3JGAwCIXRg8pxugbk6My113TnzgVY/nIyuTpoYveH2irX1+2ctvf 6/ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references:reply-to:organization; bh=OjqhXtIu4tfuUuqmTzA0h3T7qRniA71xVyU4J5hMdTE=; b=DCCjLI45qAtztAwk5RdfNPaWpwu6VRrqMZKszlSu104AeTH64SSugYaPXBFLqLhWYY bnDw8hGlUNd1B8J1tdQHjUX6vBhdwoWhdMt2OgB2HCf7o9kNJVwft1dkfu7IrQYwfciP DPU3Ud4SOQcJTHS6CKBm4qNcsRmQgXMrWcqtzxBqWIh/eAUNj7LLMlorerzg39rpIVTC DNFuUlHnMbf8KabuYQ0V+fUgK3igs5JOYsOuUwrZcGB8h7Ke+xCC5VLzBwNx6C/zrlOO vAHuftSWJl+L4VWJX82Aeg2WUxLq1YkS0ndpay0XgCmS0zG8R2IrHxeLdVAs/wjssOxk 8YYQ== X-Gm-Message-State: AMke39nIZ4MiG/m5pbHbz82Sk7+e524q5zr4D8HrT5VB4Ta+u+inMv6GiRDkR0eE7lomkA== X-Received: by 10.55.188.66 with SMTP id m63mr7909039qkf.278.1488346111317; Tue, 28 Feb 2017 21:28:31 -0800 (PST) Received: from z87.localdomain (pool-96-230-116-151.bstnma.fios.verizon.net. [96.230.116.151]) by smtp.gmail.com with ESMTPSA id c141sm2530517qkb.10.2017.02.28.21.28.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 21:28:30 -0800 (PST) From: Len Brown To: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Len Brown Subject: [PATCH 13/44] tools/power turbostat: further decode MSR_IA32_MISC_ENABLE Date: Wed, 1 Mar 2017 00:27:17 -0500 Message-Id: X-Mailer: git-send-email 2.11.0.161.g6610af872 In-Reply-To: <20170301052748.27810-1-lenb@kernel.org> References: <20170301052748.27810-1-lenb@kernel.org> In-Reply-To: <678a3bd1b3de6d2ebf604e7d708bc8150bb667e9.1488345270.git.len.brown@intel.com> References: <678a3bd1b3de6d2ebf604e7d708bc8150bb667e9.1488345270.git.len.brown@intel.com> Reply-To: Len Brown Organization: Intel Open Source Technology Center Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Len Brown Decode MISC_ENABLE.NO_TURBO, also use the #defines in msr-index.h for decoding this register cpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO) Although it is not architectural, decode also MSR_IA32_MISC_ENABLE.prefetch-disable (bit-9). documented to be present on: Core, P4, Intel-Xeon reserved on: Atom, Silvermont, Nehalem, SNB, PHI ec. Signed-off-by: Len Brown --- tools/power/x86/turbostat/turbostat.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 762b81497c3b..a1ec9d816dfa 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -3509,11 +3509,13 @@ void decode_misc_enable_msr(void) unsigned long long msr; if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) - fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n", + fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", base_cpu, msr, - msr & (1 << 3) ? "TCC" : "", - msr & (1 << 16) ? "EIST" : "", - msr & (1 << 18) ? "MONITOR" : ""); + msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", + msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", + msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "", + msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", + msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); } /*