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[net,0/6] mlx5 misc fixes 2025-03-10

Message ID 1741644104-97767-1-git-send-email-tariqt@nvidia.com (mailing list archive)
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Series mlx5 misc fixes 2025-03-10 | expand

Message

Tariq Toukan March 10, 2025, 10:01 p.m. UTC 
Hi,

This patchset provides misc bug fixes from the team to the mlx5 core and
Eth drivers.

Thanks,
Tariq.

Carolina Jubran (1):
  net/mlx5e: Prevent bridge link show failure for non-eswitch-allowed
    devices

Jianbo Liu (1):
  net/mlx5: Bridge, fix the crash caused by LAG state check

Shay Drory (2):
  net/mlx5: Fix incorrect IRQ pool usage when releasing IRQs
  net/mlx5: Lag, Check shared fdb before creating MultiPort E-Switch

Vlad Dogaru (1):
  net/mlx5: HWS, Rightsize bwc matcher priority

Yevgeny Kliteynik (1):
  net/mlx5: DR, use the right action structs for STEv3

 .../mellanox/mlx5/core/en/rep/bridge.c        | 12 ++---
 .../net/ethernet/mellanox/mlx5/core/en_main.c |  6 +--
 drivers/net/ethernet/mellanox/mlx5/core/eq.c  |  2 +-
 .../mellanox/mlx5/core/irq_affinity.c         |  2 +-
 .../net/ethernet/mellanox/mlx5/core/lag/lag.c |  4 +-
 .../net/ethernet/mellanox/mlx5/core/lag/lag.h |  1 +
 .../ethernet/mellanox/mlx5/core/lag/mpesw.c   |  3 +-
 .../ethernet/mellanox/mlx5/core/mlx5_irq.h    |  4 +-
 .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 13 +++--
 .../net/ethernet/mellanox/mlx5/core/pci_irq.h |  2 +-
 .../mellanox/mlx5/core/steering/hws/bwc.h     |  2 +-
 .../mellanox/mlx5/core/steering/sws/dr_ste.h  |  4 ++
 .../mlx5/core/steering/sws/dr_ste_v1.c        | 52 ++++++++++---------
 .../mlx5/core/steering/sws/dr_ste_v1.h        |  4 ++
 .../mlx5/core/steering/sws/dr_ste_v2.c        |  2 +
 .../mlx5/core/steering/sws/dr_ste_v3.c        | 42 +++++++++++++++
 16 files changed, 108 insertions(+), 47 deletions(-)


base-commit: 505ead7ab77f289f12d8a68ac83da068e4d4408b