From patchwork Sat Apr 23 10:26:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lijun Ou X-Patchwork-Id: 8917861 Return-Path: X-Original-To: patchwork-linux-rdma@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 84521BF29F for ; Sat, 23 Apr 2016 10:26:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 97B5120160 for ; Sat, 23 Apr 2016 10:26:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 95D0A201EF for ; Sat, 23 Apr 2016 10:26:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752176AbcDWKSP (ORCPT ); Sat, 23 Apr 2016 06:18:15 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:29568 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751918AbcDWKSO (ORCPT ); Sat, 23 Apr 2016 06:18:14 -0400 Received: from 172.24.1.60 (EHLO szxeml434-hub.china.huawei.com) ([172.24.1.60]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DFW64423; Sat, 23 Apr 2016 18:18:10 +0800 (CST) Received: from linux-ioko.site (10.71.200.31) by szxeml434-hub.china.huawei.com (10.82.67.225) with Microsoft SMTP Server id 14.3.235.1; Sat, 23 Apr 2016 18:17:58 +0800 From: Lijun Ou To: , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v5 02/21] devicetree: bindings: IB: Add binding document for HiSilicon RoCE Date: Sat, 23 Apr 2016 18:26:40 +0800 Message-ID: <1461407219-72027-3-git-send-email-oulijun@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461407219-72027-1-git-send-email-oulijun@huawei.com> References: <1461407219-72027-1-git-send-email-oulijun@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.71.200.31] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.571B4BE2.0172, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 0c025d19a2d97ff513f8fe64589697ca Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds related DTS binding document for HiSilicon RoCE driver. Signed-off-by: Lijun Ou Signed-off-by: Wei Hu(Xavier) --- .../bindings/infiniband/hisilicon-hns-roce.txt | 107 +++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt diff --git a/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt new file mode 100644 index 0000000..5180fef --- /dev/null +++ b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt @@ -0,0 +1,107 @@ +HiSilicon RoCE DT description + +HiSilicon RoCE engine is a part of network subsystem. +It works depending on other part of network wubsytem, such as, gmac and +dsa fabric. + +Additional properties are described here: + +Required properties: +- compatible: Should contain "hisilicon,hns-roce-v1". +- reg: Physical base address of the roce driver and +length of memory mapped region. +- eth-handle: phandle, specifies a reference to a node +representing a ethernet device. +- dsaf-handle: phandle, specifies a reference to a node +representing a dsaf device. +- #address-cells: must be 2 +- #size-cells: must be 2 +Optional properties: +- dma-coherent: Present if DMA operations are coherent. +- interrupt-parent: the interrupt parent of this device. +- interrupts: should contain 32 completion event irq,1 async event irq +and 1 event overflow irq. +- interrupt-names:should be one of 34 irqs for roce device + - roce_ce0_irq ~ roce_ce31_irq: 32 complete event irq + - roce_ae_irq: 1 async event irq + - roce_common_irq: named common exception warning irq +Example: + infiniband@c4000000 { + compatible = "hisilicon,hns-roce-v1"; + reg = <0x0 0xc4000000 0x0 0x100000>; + dma-coherent; + eth-handle = <ð2 ð3 ð4 ð5 ð6 ð7>; + dsaf-handle = <&soc0_dsa>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mbigen_dsa>; + interrupts = <722 1>, + <723 1>, + <724 1>, + <725 1>, + <726 1>, + <727 1>, + <728 1>, + <729 1>, + <730 1>, + <731 1>, + <732 1>, + <733 1>, + <734 1>, + <735 1>, + <736 1>, + <737 1>, + <738 1>, + <739 1>, + <740 1>, + <741 1>, + <742 1>, + <743 1>, + <744 1>, + <745 1>, + <746 1>, + <747 1>, + <748 1>, + <749 1>, + <750 1>, + <751 1>, + <752 1>, + <753 1>, + <785 1>, + <754 4>; + + interrupt-names = "roce_ce0_irq", + "roce_ce1_irq", + "roce_ce2_irq", + "roce_ce3_irq", + "roce_ce4_irq", + "roce_ce5_irq", + "roce_ce6_irq", + "roce_ce7_irq", + "roce_ce8_irq", + "roce_ce9_irq", + "roce_ce10_irq", + "roce_ce11_irq", + "roce_ce12_irq", + "roce_ce13_irq", + "roce_ce14_irq", + "roce_ce15_irq", + "roce_ce16_irq", + "roce_ce17_irq", + "roce_ce18_irq", + "roce_ce19_irq", + "roce_ce20_irq", + "roce_ce21_irq", + "roce_ce22_irq", + "roce_ce23_irq", + "roce_ce24_irq", + "roce_ce25_irq", + "roce_ce26_irq", + "roce_ce27_irq", + "roce_ce28_irq", + "roce_ce29_irq", + "roce_ce30_irq", + "roce_ce31_irq", + "roce_ae_irq", + "roce_common_irq"; + };