From patchwork Mon Jan 14 11:24:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devesh Sharma X-Patchwork-Id: 10762235 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3AD2A6C2 for ; Mon, 14 Jan 2019 11:24:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C017286A9 for ; Mon, 14 Jan 2019 11:24:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2012328821; Mon, 14 Jan 2019 11:24:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B563C286A9 for ; Mon, 14 Jan 2019 11:24:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726861AbfANLYi (ORCPT ); Mon, 14 Jan 2019 06:24:38 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:39450 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726526AbfANLYh (ORCPT ); Mon, 14 Jan 2019 06:24:37 -0500 Received: by mail-pg1-f195.google.com with SMTP id w6so9335539pgl.6 for ; Mon, 14 Jan 2019 03:24:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nsspBx07Lb9Tl5UlPuKdQ1wP4V9KQdzaXD/2tQe4fmY=; b=NUKmce1bicLhlL/bb6/FN3cXSlSbIJPrHObePPl0+sivWiLYkv9Uf7hn1+DQ5nQrn3 1JvnafU23oWXApkhMMYwgI6rPdCh/aCLOhwKoCKnAZngC8vcwg0UgODzPnkOTCjYt8e0 oHht02A6lN9++9Hee7v6AgcEL2GOATlp4JK3M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nsspBx07Lb9Tl5UlPuKdQ1wP4V9KQdzaXD/2tQe4fmY=; b=gXMkaHcU1iaVjRp4roqR85beyUsHmwBDn+jKp7znUqwtuth5paEYMivX8r65hAlhfi aLGtc3hUdu9v8s85ewzy+IPFRafLzK9NRTBZd/NVw603wL48IZriGvQ+YWYwYJbfFbI1 1fdcT/Gg4iitymXVNwWzGhEMJ/e56vYonCMIdyi/pbTyYizAteNtAE1oXB6qAYNJAl0w 0gdFIFVLtjEtTAOtGJQ199IxwQ9lRsDF1jZ677GLNKgqVS+6zrstPZYE9OvcvCVgtx61 Ul4YJiuJ16GcNiUFaJjs3q8L5DEcWCjmiyK2rha3FKeS6dHkqnPJBkNe7ALEjEyMu2cz 9tEA== X-Gm-Message-State: AJcUukdvcgPjFbT86OMcHsl9SoZJvy3567+xomzl9mn/hr9My365auR+ kPbBfG4qClrkbdVWeBJ//Q6fT7AFwHSx3ExfFGfs2fowY1gsnyciTCtIe5KjRGVAb2eIKcFN+Zp MG4D38oEPtcs+A67m/ftPfNSNcp2og3Rr/g6GVV7M+qTzHAvUVSpWVKtBB8Qd6/b/ocw4ygaiEw zFNK8= X-Google-Smtp-Source: ALg8bN5TpDeNeqRcumHYa4TFYT485SLZCkow6MJ1npkehrziVWCGNwdmc4Jv+PaMeROrkp/FyAtTYw== X-Received: by 2002:a62:9657:: with SMTP id c84mr25574960pfe.77.1547465076202; Mon, 14 Jan 2019 03:24:36 -0800 (PST) Received: from neo00-el73.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id z10sm268894pfg.120.2019.01.14.03.24.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jan 2019 03:24:35 -0800 (PST) From: Devesh Sharma To: linux-rdma@vger.kernel.org Cc: dledford@redhat.com, jgg@mellanox.com, Devesh Sharma Subject: [for-next V2 6/7] RDMA/bnxt_re: Update kernel user abi to pass chip context Date: Mon, 14 Jan 2019 06:24:11 -0500 Message-Id: <1547465052-7622-7-git-send-email-devesh.sharma@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1547465052-7622-1-git-send-email-devesh.sharma@broadcom.com> References: <1547465052-7622-1-git-send-email-devesh.sharma@broadcom.com> Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP User space verbs provider library would need chip context. Changing the ABI to add chip version details in structure. Furthermore, changing the kernel driver ucontext allocation code to initialize the abi structure with appropriate values. As suggested by community, appended the new fields at the bottom of the ABI structure and retaining to older fields as those were in the older versions. Signed-off-by: Devesh Sharma --- drivers/infiniband/hw/bnxt_re/ib_verbs.c | 17 ++++++++++++++--- include/uapi/rdma/bnxt_re-abi.h | 7 ++++++- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/hw/bnxt_re/ib_verbs.c index 02ccd2f..271f022 100644 --- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c +++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c @@ -3695,9 +3695,10 @@ struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev, struct ib_udata *udata) { struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); + struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; struct bnxt_re_uctx_resp resp; struct bnxt_re_ucontext *uctx; - struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; + u32 chip_met_rev_num = 0; int rc; dev_dbg(rdev_to_dev(rdev), "ABI version requested %d", @@ -3721,8 +3722,18 @@ struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev, goto fail; } spin_lock_init(&uctx->sh_lock); - - resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/ + if (BNXT_RE_ABI_VERSION >= 2) { + chip_met_rev_num = rdev->chip_ctx.chip_num; + chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_rev & 0xFF) << + BNXT_RE_CHIP_ID0_CHIP_REV_SFT; + chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_metal & 0xFF) << + BNXT_RE_CHIP_ID0_CHIP_MET_SFT; + resp.chip_id0 = chip_met_rev_num; + /* Future extension of chip info */ + resp.chip_id1 = 0; + } + /*Temp, Use idr_alloc instead */ + resp.dev_id = rdev->en_dev->pdev->devfn; resp.max_qp = rdev->qplib_ctx.qpc_count; resp.pg_size = PAGE_SIZE; resp.cqe_sz = sizeof(struct cq_base); diff --git a/include/uapi/rdma/bnxt_re-abi.h b/include/uapi/rdma/bnxt_re-abi.h index a7a6111..1cc63e7 100644 --- a/include/uapi/rdma/bnxt_re-abi.h +++ b/include/uapi/rdma/bnxt_re-abi.h @@ -42,14 +42,19 @@ #include -#define BNXT_RE_ABI_VERSION 1 +#define BNXT_RE_ABI_VERSION 2 +#define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00 +#define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10 +#define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18 struct bnxt_re_uctx_resp { __u32 dev_id; __u32 max_qp; __u32 pg_size; __u32 cqe_sz; __u32 max_cqd; + __u32 chip_id0; + __u32 chip_id1; __u32 rsvd; };