@@ -54,6 +54,7 @@
/* Hardware specification only for v1 engine */
#define HNS_ROCE_MIN_CQE_NUM 0x40
#define HNS_ROCE_MIN_WQE_NUM 0x20
+#define HNS_ROCE_MIN_SRQ_WQE_NUM 1
/* Hardware specification only for v1 engine */
#define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
@@ -860,7 +860,7 @@ int hns_roce_srqwq_overflow(struct hns_roce_srq *srq, int nreq)
unsigned int cur;
cur = idx_que->head - idx_que->tail;
- return cur + nreq >= srq->wqe_cnt - 1;
+ return cur + nreq >= srq->wqe_cnt;
}
static int find_empty_entry(struct hns_roce_idx_que *idx_que,
@@ -5338,7 +5338,7 @@ static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
return -EINVAL;
if (srq_attr_mask & IB_SRQ_LIMIT) {
- if (srq_attr->srq_limit >= srq->wqe_cnt)
+ if (srq_attr->srq_limit > srq->wqe_cnt)
return -EINVAL;
mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
@@ -5401,7 +5401,7 @@ static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
SRQC_BYTE_8_SRQ_LIMIT_WL_S);
attr->srq_limit = limit_wl;
- attr->max_wr = srq->wqe_cnt - 1;
+ attr->max_wr = srq->wqe_cnt;
attr->max_sge = srq->max_gs - srq->rsv_sge;
out:
@@ -320,7 +320,7 @@ int hns_roce_create_srq(struct ib_srq *ib_srq,
max_sge = proc_srq_sge(hr_dev, srq, !!udata);
- if (init_attr->attr.max_wr >= hr_dev->caps.max_srq_wrs ||
+ if (init_attr->attr.max_wr > hr_dev->caps.max_srq_wrs ||
init_attr->attr.max_sge > max_sge) {
ibdev_err(&hr_dev->ib_dev,
"SRQ config error, depth = %u, sge = %d\n",
@@ -331,7 +331,9 @@ int hns_roce_create_srq(struct ib_srq *ib_srq,
mutex_init(&srq->mutex);
spin_lock_init(&srq->lock);
- srq->wqe_cnt = roundup_pow_of_two(init_attr->attr.max_wr + 1);
+ init_attr->attr.max_wr = max_t(u32, init_attr->attr.max_wr,
+ HNS_ROCE_MIN_SRQ_WQE_NUM);
+ srq->wqe_cnt = roundup_pow_of_two(init_attr->attr.max_wr);
srq->max_gs =
roundup_pow_of_two(init_attr->attr.max_sge + srq->rsv_sge);
init_attr->attr.max_wr = srq->wqe_cnt;