Message ID | 1631470526-22228-5-git-send-email-selvin.xavier@broadcom.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Leon Romanovsky |
Headers | show |
Series | RDMA/bnxt_re: Driver update | expand |
On Sun, Sep 12, 2021 at 11:15:18AM -0700, Selvin Xavier wrote: > Driver has 1ms delay between the polling for atomic command completion. > Polling immediately after issuing command usually doesn't report > any completions. So all commands in the blocking path needs two > iterations. So effectively 1ms spend on each command. HW requires > much lesser time for each command. So reduce the delay to 1us > and increase the iteration count to wait for the same time. > > Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> > --- > drivers/infiniband/hw/bnxt_re/qplib_rcfw.c | 2 +- > drivers/infiniband/hw/bnxt_re/qplib_rcfw.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > Thanks, Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c index 5d384de..947e8c5 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c +++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c @@ -78,7 +78,7 @@ static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) if (!test_bit(cbit, cmdq->cmdq_bitmap)) goto done; do { - mdelay(1); /* 1m sec */ + udelay(1); bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet); } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count); done: diff --git a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h index 9474c00..82faa4e 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h +++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h @@ -96,7 +96,7 @@ static inline void bnxt_qplib_set_cmd_slots(struct cmdq_base *req) #define RCFW_MAX_COOKIE_VALUE 0x7FFF #define RCFW_CMD_IS_BLOCKING 0x8000 -#define RCFW_BLOCKED_CMD_WAIT_COUNT 0x4E20 +#define RCFW_BLOCKED_CMD_WAIT_COUNT 20000000UL /* 20 sec */ #define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL
Driver has 1ms delay between the polling for atomic command completion. Polling immediately after issuing command usually doesn't report any completions. So all commands in the blocking path needs two iterations. So effectively 1ms spend on each command. HW requires much lesser time for each command. So reduce the delay to 1us and increase the iteration count to wait for the same time. Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> --- drivers/infiniband/hw/bnxt_re/qplib_rcfw.c | 2 +- drivers/infiniband/hw/bnxt_re/qplib_rcfw.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)