Message ID | 20201120230339.651609-4-saeedm@nvidia.com (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show |
Series | mlx5 next updates 2020-11-20 | expand |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c index 7df883686d46..1b3b2acd45c5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c @@ -630,7 +630,7 @@ static int dr_matcher_init(struct mlx5dr_matcher *matcher, } if (mask) { - if (mask->match_sz > sizeof(struct mlx5dr_match_param)) { + if (mask->match_sz > DR_SZ_MATCH_PARAM) { mlx5dr_err(dmn, "Invalid match size attribute\n"); return -EINVAL; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c index b3c9dc032026..6d73719db1f4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c @@ -874,8 +874,7 @@ static bool dr_rule_verify(struct mlx5dr_matcher *matcher, u32 s_idx, e_idx; if (!value_size || - (value_size > sizeof(struct mlx5dr_match_param) || - (value_size % sizeof(u32)))) { + (value_size > DR_SZ_MATCH_PARAM || (value_size % sizeof(u32)))) { mlx5dr_err(matcher->tbl->dmn, "Rule parameters length is incorrect\n"); return false; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h index f50f3b107aa3..937f469ec678 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h @@ -17,6 +17,7 @@ #define WIRE_PORT 0xFFFF #define DR_STE_SVLAN 0x1 #define DR_STE_CVLAN 0x2 +#define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4) #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)