From patchwork Fri Nov 20 23:03:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saeed Mahameed X-Patchwork-Id: 11922799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2000C8300C for ; Fri, 20 Nov 2020 23:04:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 791832415B for ; Fri, 20 Nov 2020 23:04:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="FujR3Ca0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728444AbgKTXEG (ORCPT ); Fri, 20 Nov 2020 18:04:06 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:12663 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727766AbgKTXEG (ORCPT ); Fri, 20 Nov 2020 18:04:06 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 20 Nov 2020 15:04:09 -0800 Received: from sx1.mtl.com (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 20 Nov 2020 23:03:58 +0000 From: Saeed Mahameed To: Saeed Mahameed , Leon Romanovsky CC: , , Eran Ben Elisha , Tariq Toukan Subject: [PATCH mlx5-next 05/16] net/mlx5: Add ts_cqe_to_dest_cqn related bits Date: Fri, 20 Nov 2020 15:03:28 -0800 Message-ID: <20201120230339.651609-6-saeedm@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201120230339.651609-1-saeedm@nvidia.com> References: <20201120230339.651609-1-saeedm@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1605913449; bh=CCGWpDtXxqoygsnIR7vhCC37Ppe39mjFJh+AdZfJYWg=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:Content-Type: X-Originating-IP:X-ClientProxiedBy; b=FujR3Ca0Zdoq1ysZQq5LLB/MGi5Q3vnGcD3M/GK7CKMjACm2bw65Z+PDRQy9TtpXd ep457Xph9mx5Fndr3aGfASUc5ByY4hxrwVr0EZjxp21/5UgAWzBNOCo+1qfEM9Pk3M I1t0ie5mHJf0X4E9IHZEvx3a0QXVwlYyQed3Y9wrrk2Ie0baA+qTWVmm9v7azfB3JU VXNuw5DVvKZSumY0wlsY0izbu5miBd6Qr85ZzjXdjVHHuuT+gQBn5QsdxM5KcJAAG7 sr1mhvo5l/RodJnWcoGIQCGqmITMZ94nnabogfypGgxM81Yah5rIn2QI4d+E+KvSKk lAiuY/uvUmhKA== Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Eran Ben Elisha Add a bit in HCA capabilities layout to indicate if ts_cqe_to_dest_cqn is supported. In addition, add ts_cqe_to_dest_cqn field to SQ context, for driver to set the actual CQN. Signed-off-by: Eran Ben Elisha Reviewed-by: Tariq Toukan Signed-off-by: Saeed Mahameed --- include/linux/mlx5/mlx5_ifc.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 11c24fafd7f2..632b9a61fda5 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1261,7 +1261,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 ece_support[0x1]; u8 reserved_at_a4[0x7]; u8 log_max_srq[0x5]; - u8 reserved_at_b0[0x10]; + u8 reserved_at_b0[0x2]; + u8 ts_cqe_to_dest_cqn[0x1]; + u8 reserved_at_b3[0xd]; u8 max_sgl_for_optimized_performance[0x8]; u8 log_max_cq_sz[0x8]; @@ -3312,8 +3314,12 @@ struct mlx5_ifc_sqc_bits { u8 reserved_at_80[0x10]; u8 hairpin_peer_vhca[0x10]; - u8 reserved_at_a0[0x50]; + u8 reserved_at_a0[0x20]; + u8 reserved_at_c0[0x8]; + u8 ts_cqe_to_dest_cqn[0x18]; + + u8 reserved_at_e0[0x10]; u8 packet_pacing_rate_limit_index[0x10]; u8 tis_lst_sz[0x10]; u8 reserved_at_110[0x10];