| Message ID | 20220917031104.21222-11-rpearsonhpe@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Implement the xrc transport | expand |
Hi Bob,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on db77d84cfe3608eac938302f8f7178e44415bcba]
url: https://github.com/intel-lab-lkp/linux/commits/Bob-Pearson/Implement-the-xrc-transport/20220917-111448
base: db77d84cfe3608eac938302f8f7178e44415bcba
config: riscv-randconfig-r032-20220921
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/34e962233dad1c9c83d13c8211758b1861cde89e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Bob-Pearson/Implement-the-xrc-transport/20220917-111448
git checkout 34e962233dad1c9c83d13c8211758b1861cde89e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/cxl/core/ drivers/infiniband/sw/rxe/ kernel/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/infiniband/sw/rxe/rxe_comp.c:247:10: error: label at end of compound statement: expected statement
default:
^
;
1 error generated.
vim +247 drivers/infiniband/sw/rxe/rxe_comp.c
8700e3e7c4857d Moni Shoua 2016-06-16 211
8700e3e7c4857d Moni Shoua 2016-06-16 212 static inline enum comp_state check_ack(struct rxe_qp *qp,
8700e3e7c4857d Moni Shoua 2016-06-16 213 struct rxe_pkt_info *pkt,
8700e3e7c4857d Moni Shoua 2016-06-16 214 struct rxe_send_wqe *wqe)
8700e3e7c4857d Moni Shoua 2016-06-16 215 {
34e962233dad1c Bob Pearson 2022-09-16 216 struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
8700e3e7c4857d Moni Shoua 2016-06-16 217 unsigned int mask = pkt->mask;
34e962233dad1c Bob Pearson 2022-09-16 218 int opcode;
8700e3e7c4857d Moni Shoua 2016-06-16 219 u8 syn;
8700e3e7c4857d Moni Shoua 2016-06-16 220
34e962233dad1c Bob Pearson 2022-09-16 221 /* Mask off type bits and check the sequence only */
34e962233dad1c Bob Pearson 2022-09-16 222 switch (qp->comp.opcode & IB_OPCODE_CMD) {
8700e3e7c4857d Moni Shoua 2016-06-16 223 case -1:
8700e3e7c4857d Moni Shoua 2016-06-16 224 /* Will catch all *_ONLY cases. */
4c69706b3f2210 Bob Pearson 2022-09-16 225 if (!(mask & RXE_FIRST_MASK))
8700e3e7c4857d Moni Shoua 2016-06-16 226 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 227
8700e3e7c4857d Moni Shoua 2016-06-16 228 break;
8700e3e7c4857d Moni Shoua 2016-06-16 229
34e962233dad1c Bob Pearson 2022-09-16 230 case IB_OPCODE_RDMA_READ_RESPONSE_FIRST:
34e962233dad1c Bob Pearson 2022-09-16 231 case IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE:
34e962233dad1c Bob Pearson 2022-09-16 232 opcode = pkt->opcode & IB_OPCODE_CMD;
34e962233dad1c Bob Pearson 2022-09-16 233 if (opcode != IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE &&
34e962233dad1c Bob Pearson 2022-09-16 234 opcode != IB_OPCODE_RDMA_READ_RESPONSE_LAST) {
030e46e495af85 Vijay Immanuel 2018-06-13 235 /* read retries of partial data may restart from
030e46e495af85 Vijay Immanuel 2018-06-13 236 * read response first or response only.
030e46e495af85 Vijay Immanuel 2018-06-13 237 */
030e46e495af85 Vijay Immanuel 2018-06-13 238 if ((pkt->psn == wqe->first_psn &&
34e962233dad1c Bob Pearson 2022-09-16 239 opcode == IB_OPCODE_RDMA_READ_RESPONSE_FIRST) ||
030e46e495af85 Vijay Immanuel 2018-06-13 240 (wqe->first_psn == wqe->last_psn &&
34e962233dad1c Bob Pearson 2022-09-16 241 opcode == IB_OPCODE_RDMA_READ_RESPONSE_ONLY))
030e46e495af85 Vijay Immanuel 2018-06-13 242 break;
030e46e495af85 Vijay Immanuel 2018-06-13 243
8700e3e7c4857d Moni Shoua 2016-06-16 244 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 245 }
8700e3e7c4857d Moni Shoua 2016-06-16 246 break;
8700e3e7c4857d Moni Shoua 2016-06-16 @247 default:
34e962233dad1c Bob Pearson 2022-09-16 248 //WARN_ON_ONCE(1);
8700e3e7c4857d Moni Shoua 2016-06-16 249 }
8700e3e7c4857d Moni Shoua 2016-06-16 250
34e962233dad1c Bob Pearson 2022-09-16 251 /* Mask off the type bits and check operation validity. */
34e962233dad1c Bob Pearson 2022-09-16 252 switch (pkt->opcode & IB_OPCODE_CMD) {
34e962233dad1c Bob Pearson 2022-09-16 253 case IB_OPCODE_RDMA_READ_RESPONSE_FIRST:
34e962233dad1c Bob Pearson 2022-09-16 254 case IB_OPCODE_RDMA_READ_RESPONSE_LAST:
34e962233dad1c Bob Pearson 2022-09-16 255 case IB_OPCODE_RDMA_READ_RESPONSE_ONLY:
8700e3e7c4857d Moni Shoua 2016-06-16 256 syn = aeth_syn(pkt);
8700e3e7c4857d Moni Shoua 2016-06-16 257
8700e3e7c4857d Moni Shoua 2016-06-16 258 if ((syn & AETH_TYPE_MASK) != AETH_ACK)
8700e3e7c4857d Moni Shoua 2016-06-16 259 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 260
df561f6688fef7 Gustavo A. R. Silva 2020-08-23 261 fallthrough;
34e962233dad1c Bob Pearson 2022-09-16 262 case IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE:
8700e3e7c4857d Moni Shoua 2016-06-16 263 if (wqe->wr.opcode != IB_WR_RDMA_READ &&
8700e3e7c4857d Moni Shoua 2016-06-16 264 wqe->wr.opcode != IB_WR_RDMA_READ_WITH_INV) {
61b717d041b197 Bart Van Assche 2018-06-26 265 wqe->status = IB_WC_FATAL_ERR;
8700e3e7c4857d Moni Shoua 2016-06-16 266 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 267 }
8700e3e7c4857d Moni Shoua 2016-06-16 268 reset_retry_counters(qp);
8700e3e7c4857d Moni Shoua 2016-06-16 269 return COMPST_READ;
8700e3e7c4857d Moni Shoua 2016-06-16 270
34e962233dad1c Bob Pearson 2022-09-16 271 case IB_OPCODE_ATOMIC_ACKNOWLEDGE:
8700e3e7c4857d Moni Shoua 2016-06-16 272 syn = aeth_syn(pkt);
8700e3e7c4857d Moni Shoua 2016-06-16 273
8700e3e7c4857d Moni Shoua 2016-06-16 274 if ((syn & AETH_TYPE_MASK) != AETH_ACK)
8700e3e7c4857d Moni Shoua 2016-06-16 275 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 276
8700e3e7c4857d Moni Shoua 2016-06-16 277 if (wqe->wr.opcode != IB_WR_ATOMIC_CMP_AND_SWP &&
8700e3e7c4857d Moni Shoua 2016-06-16 278 wqe->wr.opcode != IB_WR_ATOMIC_FETCH_AND_ADD)
8700e3e7c4857d Moni Shoua 2016-06-16 279 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 280 reset_retry_counters(qp);
8700e3e7c4857d Moni Shoua 2016-06-16 281 return COMPST_ATOMIC;
8700e3e7c4857d Moni Shoua 2016-06-16 282
34e962233dad1c Bob Pearson 2022-09-16 283 case IB_OPCODE_ACKNOWLEDGE:
8700e3e7c4857d Moni Shoua 2016-06-16 284 syn = aeth_syn(pkt);
8700e3e7c4857d Moni Shoua 2016-06-16 285 switch (syn & AETH_TYPE_MASK) {
8700e3e7c4857d Moni Shoua 2016-06-16 286 case AETH_ACK:
8700e3e7c4857d Moni Shoua 2016-06-16 287 reset_retry_counters(qp);
8700e3e7c4857d Moni Shoua 2016-06-16 288 return COMPST_WRITE_SEND;
8700e3e7c4857d Moni Shoua 2016-06-16 289
8700e3e7c4857d Moni Shoua 2016-06-16 290 case AETH_RNR_NAK:
0b1e5b99a48b5b Yonatan Cohen 2017-03-10 291 rxe_counter_inc(rxe, RXE_CNT_RCV_RNR);
8700e3e7c4857d Moni Shoua 2016-06-16 292 return COMPST_RNR_RETRY;
8700e3e7c4857d Moni Shoua 2016-06-16 293
8700e3e7c4857d Moni Shoua 2016-06-16 294 case AETH_NAK:
8700e3e7c4857d Moni Shoua 2016-06-16 295 switch (syn) {
8700e3e7c4857d Moni Shoua 2016-06-16 296 case AETH_NAK_PSN_SEQ_ERROR:
8700e3e7c4857d Moni Shoua 2016-06-16 297 /* a nak implicitly acks all packets with psns
8700e3e7c4857d Moni Shoua 2016-06-16 298 * before
8700e3e7c4857d Moni Shoua 2016-06-16 299 */
8700e3e7c4857d Moni Shoua 2016-06-16 300 if (psn_compare(pkt->psn, qp->comp.psn) > 0) {
0b1e5b99a48b5b Yonatan Cohen 2017-03-10 301 rxe_counter_inc(rxe,
0b1e5b99a48b5b Yonatan Cohen 2017-03-10 302 RXE_CNT_RCV_SEQ_ERR);
8700e3e7c4857d Moni Shoua 2016-06-16 303 qp->comp.psn = pkt->psn;
8700e3e7c4857d Moni Shoua 2016-06-16 304 if (qp->req.wait_psn) {
8700e3e7c4857d Moni Shoua 2016-06-16 305 qp->req.wait_psn = 0;
8ac0e6641c7ca1 Zhu Yanjun 2020-02-12 306 rxe_run_task(&qp->req.task, 0);
8700e3e7c4857d Moni Shoua 2016-06-16 307 }
8700e3e7c4857d Moni Shoua 2016-06-16 308 }
8700e3e7c4857d Moni Shoua 2016-06-16 309 return COMPST_ERROR_RETRY;
8700e3e7c4857d Moni Shoua 2016-06-16 310
8700e3e7c4857d Moni Shoua 2016-06-16 311 case AETH_NAK_INVALID_REQ:
8700e3e7c4857d Moni Shoua 2016-06-16 312 wqe->status = IB_WC_REM_INV_REQ_ERR;
8700e3e7c4857d Moni Shoua 2016-06-16 313 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 314
8700e3e7c4857d Moni Shoua 2016-06-16 315 case AETH_NAK_REM_ACC_ERR:
8700e3e7c4857d Moni Shoua 2016-06-16 316 wqe->status = IB_WC_REM_ACCESS_ERR;
8700e3e7c4857d Moni Shoua 2016-06-16 317 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 318
8700e3e7c4857d Moni Shoua 2016-06-16 319 case AETH_NAK_REM_OP_ERR:
8700e3e7c4857d Moni Shoua 2016-06-16 320 wqe->status = IB_WC_REM_OP_ERR;
8700e3e7c4857d Moni Shoua 2016-06-16 321 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 322
8700e3e7c4857d Moni Shoua 2016-06-16 323 default:
8700e3e7c4857d Moni Shoua 2016-06-16 324 pr_warn("unexpected nak %x\n", syn);
8700e3e7c4857d Moni Shoua 2016-06-16 325 wqe->status = IB_WC_REM_OP_ERR;
8700e3e7c4857d Moni Shoua 2016-06-16 326 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 327 }
8700e3e7c4857d Moni Shoua 2016-06-16 328
8700e3e7c4857d Moni Shoua 2016-06-16 329 default:
8700e3e7c4857d Moni Shoua 2016-06-16 330 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 331 }
8700e3e7c4857d Moni Shoua 2016-06-16 332 break;
8700e3e7c4857d Moni Shoua 2016-06-16 333
8700e3e7c4857d Moni Shoua 2016-06-16 334 default:
8700e3e7c4857d Moni Shoua 2016-06-16 335 pr_warn("unexpected opcode\n");
8700e3e7c4857d Moni Shoua 2016-06-16 336 }
8700e3e7c4857d Moni Shoua 2016-06-16 337
8700e3e7c4857d Moni Shoua 2016-06-16 338 return COMPST_ERROR;
8700e3e7c4857d Moni Shoua 2016-06-16 339 }
8700e3e7c4857d Moni Shoua 2016-06-16 340
diff --git a/drivers/infiniband/sw/rxe/rxe_comp.c b/drivers/infiniband/sw/rxe/rxe_comp.c index 1f10ae4a35d5..cb6621b4055d 100644 --- a/drivers/infiniband/sw/rxe/rxe_comp.c +++ b/drivers/infiniband/sw/rxe/rxe_comp.c @@ -213,12 +213,13 @@ static inline enum comp_state check_ack(struct rxe_qp *qp, struct rxe_pkt_info *pkt, struct rxe_send_wqe *wqe) { + struct rxe_dev *rxe = to_rdev(qp->ibqp.device); unsigned int mask = pkt->mask; + int opcode; u8 syn; - struct rxe_dev *rxe = to_rdev(qp->ibqp.device); - /* Check the sequence only */ - switch (qp->comp.opcode) { + /* Mask off type bits and check the sequence only */ + switch (qp->comp.opcode & IB_OPCODE_CMD) { case -1: /* Will catch all *_ONLY cases. */ if (!(mask & RXE_FIRST_MASK)) @@ -226,42 +227,39 @@ static inline enum comp_state check_ack(struct rxe_qp *qp, break; - case IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST: - case IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE: - if (pkt->opcode != IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE && - pkt->opcode != IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST) { + case IB_OPCODE_RDMA_READ_RESPONSE_FIRST: + case IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE: + opcode = pkt->opcode & IB_OPCODE_CMD; + if (opcode != IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE && + opcode != IB_OPCODE_RDMA_READ_RESPONSE_LAST) { /* read retries of partial data may restart from * read response first or response only. */ if ((pkt->psn == wqe->first_psn && - pkt->opcode == - IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST) || + opcode == IB_OPCODE_RDMA_READ_RESPONSE_FIRST) || (wqe->first_psn == wqe->last_psn && - pkt->opcode == - IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY)) + opcode == IB_OPCODE_RDMA_READ_RESPONSE_ONLY)) break; return COMPST_ERROR; } break; default: - WARN_ON_ONCE(1); + //WARN_ON_ONCE(1); } - /* Check operation validity. */ - switch (pkt->opcode) { - case IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST: - case IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST: - case IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY: + /* Mask off the type bits and check operation validity. */ + switch (pkt->opcode & IB_OPCODE_CMD) { + case IB_OPCODE_RDMA_READ_RESPONSE_FIRST: + case IB_OPCODE_RDMA_READ_RESPONSE_LAST: + case IB_OPCODE_RDMA_READ_RESPONSE_ONLY: syn = aeth_syn(pkt); if ((syn & AETH_TYPE_MASK) != AETH_ACK) return COMPST_ERROR; fallthrough; - /* (IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE doesn't have an AETH) - */ - case IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE: + case IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE: if (wqe->wr.opcode != IB_WR_RDMA_READ && wqe->wr.opcode != IB_WR_RDMA_READ_WITH_INV) { wqe->status = IB_WC_FATAL_ERR; @@ -270,7 +268,7 @@ static inline enum comp_state check_ack(struct rxe_qp *qp, reset_retry_counters(qp); return COMPST_READ; - case IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE: + case IB_OPCODE_ATOMIC_ACKNOWLEDGE: syn = aeth_syn(pkt); if ((syn & AETH_TYPE_MASK) != AETH_ACK) @@ -282,7 +280,7 @@ static inline enum comp_state check_ack(struct rxe_qp *qp, reset_retry_counters(qp); return COMPST_ATOMIC; - case IB_OPCODE_RC_ACKNOWLEDGE: + case IB_OPCODE_ACKNOWLEDGE: syn = aeth_syn(pkt); switch (syn & AETH_TYPE_MASK) { case AETH_ACK: @@ -669,7 +667,8 @@ int rxe_completer(void *arg) * timeouts but try to keep them as few as possible) * (4) the timeout parameter is set */ - if ((qp_type(qp) == IB_QPT_RC) && + if ((qp_type(qp) == IB_QPT_RC || + qp_type(qp) == IB_QPT_XRC_INI) && (qp->req.state == QP_STATE_READY) && (psn_compare(qp->req.psn, qp->comp.psn) > 0) && qp->qp_timeout_jiffies)
Extend code in rxe_comp.c to support xrc qp types. Signed-off-by: Bob Pearson <rpearsonhpe@gmail.com> --- drivers/infiniband/sw/rxe/rxe_comp.c | 45 ++++++++++++++-------------- 1 file changed, 22 insertions(+), 23 deletions(-)