[for-next,v2,04/13] RDMA/rxe: Extend opcodes and headers to support xrc

Message ID	20220929170836.17838-5-rpearsonhpe@gmail.com (mailing list archive)
State	Changes Requested
Delegated to:	Jason Gunthorpe
Headers	show Return-Path: <linux-rdma-owner@kernel.org> From: Bob Pearson <rpearsonhpe@gmail.com> To: jgg@nvidia.com, zyjzyj2000@gmail.com, linux-rdma@vger.kernel.org Cc: Bob Pearson <rpearsonhpe@gmail.com> Subject: [PATCH for-next v2 04/13] RDMA/rxe: Extend opcodes and headers to support xrc Date: Thu, 29 Sep 2022 12:08:28 -0500 Message-Id: <20220929170836.17838-5-rpearsonhpe@gmail.com> In-Reply-To: <20220929170836.17838-1-rpearsonhpe@gmail.com> References: <20220929170836.17838-1-rpearsonhpe@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Implement the xrc transport \| expand [for-next,v2,00/13] Implement the xrc transport [for-next,v2,01/13] RDMA/rxe: Replace START->FIRST, END->LAST [for-next,v2,02/13] RDMA/rxe: Move next_opcode() to rxe_opcode.c [for-next,v2,03/13] RDMA: Add xrc opcodes to ib_pack.h [for-next,v2,04/13] RDMA/rxe: Extend opcodes and headers to support xrc [for-next,v2,05/13] RDMA/rxe: Add xrc opcodes to next_opcode() [for-next,v2,06/13] RDMA/rxe: Implement open_xrcd and close_xrcd [for-next,v2,07/13] RDMA/rxe: Extend srq verbs to support xrcd [for-next,v2,08/13] RDMA/rxe: Extend rxe_qp.c to support xrc qps [for-next,v2,09/13] RDMA/rxe: Extend rxe_recv.c to support xrc [for-next,v2,10/13] RDMA/rxe: Extend rxe_comp.c to support xrc qps [for-next,v2,11/13] RDMA/rxe: Extend rxe_req.c to support xrc qps [for-next,v2,12/13] RDMA/rxe: Extend rxe_net.c to support xrc qps [for-next,v2,13/13] RDMA/rxe: Extend rxe_resp.c to support xrc qps

diff --git a/drivers/infiniband/sw/rxe/rxe_hdr.h b/drivers/infiniband/sw/rxe/rxe_hdr.h index e432f9e37795..e947bcf75209 100644 --- a/drivers/infiniband/sw/rxe/rxe_hdr.h +++ b/drivers/infiniband/sw/rxe/rxe_hdr.h @@ -900,6 +900,41 @@ static inline void ieth_set_rkey(struct rxe_pkt_info *pkt, u32 rkey) rxe_opcode[pkt->opcode].offset[RXE_IETH], rkey); } +/****************************************************************************** + * XRC Extended Transport Header + ******************************************************************************/ +struct rxe_xrceth { + __be32 srqn; +}; + +#define XRCETH_SRQN_MASK (0x00ffffff) + +static inline u32 __xrceth_srqn(void *arg) +{ + struct rxe_xrceth *xrceth = arg; + + return be32_to_cpu(xrceth->srqn); +} + +static inline void __xrceth_set_srqn(void *arg, u32 srqn) +{ + struct rxe_xrceth *xrceth = arg; + + xrceth->srqn = cpu_to_be32(srqn & XRCETH_SRQN_MASK); +} + +static inline u32 xrceth_srqn(struct rxe_pkt_info *pkt) +{ + return __xrceth_srqn(pkt->hdr + + rxe_opcode[pkt->opcode].offset[RXE_XRCETH]); +} + +static inline void xrceth_set_srqn(struct rxe_pkt_info *pkt, u32 srqn) +{ + __xrceth_set_srqn(pkt->hdr + + rxe_opcode[pkt->opcode].offset[RXE_XRCETH], srqn); +} + enum rxe_hdr_length { RXE_BTH_BYTES = sizeof(struct rxe_bth), RXE_DETH_BYTES = sizeof(struct rxe_deth), @@ -909,6 +944,7 @@ enum rxe_hdr_length { RXE_ATMACK_BYTES = sizeof(struct rxe_atmack), RXE_ATMETH_BYTES = sizeof(struct rxe_atmeth), RXE_IETH_BYTES = sizeof(struct rxe_ieth), + RXE_XRCETH_BYTES = sizeof(struct rxe_xrceth), RXE_RDETH_BYTES = sizeof(struct rxe_rdeth), }; diff --git a/drivers/infiniband/sw/rxe/rxe_opcode.c b/drivers/infiniband/sw/rxe/rxe_opcode.c index 6b1a1f197c4d..4ae926a37ef8 100644 --- a/drivers/infiniband/sw/rxe/rxe_opcode.c +++ b/drivers/infiniband/sw/rxe/rxe_opcode.c @@ -15,51 +15,58 @@ struct rxe_wr_opcode_info rxe_wr_opcode_info[] = { [IB_WR_RDMA_WRITE] = { .name = "IB_WR_RDMA_WRITE", .mask = { - [IB_QPT_RC] = WR_INLINE_MASK | WR_WRITE_MASK, - [IB_QPT_UC] = WR_INLINE_MASK | WR_WRITE_MASK, + [IB_QPT_RC] = WR_INLINE_MASK | WR_WRITE_MASK, + [IB_QPT_UC] = WR_INLINE_MASK | WR_WRITE_MASK, + [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_WRITE_MASK, }, }, [IB_WR_RDMA_WRITE_WITH_IMM] = { .name = "IB_WR_RDMA_WRITE_WITH_IMM", .mask = { - [IB_QPT_RC] = WR_INLINE_MASK | WR_WRITE_MASK, - [IB_QPT_UC] = WR_INLINE_MASK | WR_WRITE_MASK, + [IB_QPT_RC] = WR_INLINE_MASK | WR_WRITE_MASK, + [IB_QPT_UC] = WR_INLINE_MASK | WR_WRITE_MASK, + [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_WRITE_MASK, }, }, [IB_WR_SEND] = { .name = "IB_WR_SEND", .mask = { - [IB_QPT_GSI] = WR_INLINE_MASK | WR_SEND_MASK, - [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK, - [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK, - [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_GSI] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_SEND_MASK, }, }, [IB_WR_SEND_WITH_IMM] = { .name = "IB_WR_SEND_WITH_IMM", .mask = { - [IB_QPT_GSI] = WR_INLINE_MASK | WR_SEND_MASK, - [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK, - [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK, - [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_GSI] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_SEND_MASK, }, }, [IB_WR_RDMA_READ] = { .name = "IB_WR_RDMA_READ", .mask = { - [IB_QPT_RC] = WR_READ_MASK, + [IB_QPT_RC] = WR_READ_MASK, + [IB_QPT_XRC_INI] = WR_READ_MASK, }, }, [IB_WR_ATOMIC_CMP_AND_SWP] = { .name = "IB_WR_ATOMIC_CMP_AND_SWP", .mask = { - [IB_QPT_RC] = WR_ATOMIC_MASK, + [IB_QPT_RC] = WR_ATOMIC_MASK, + [IB_QPT_XRC_INI] = WR_ATOMIC_MASK, }, }, [IB_WR_ATOMIC_FETCH_AND_ADD] = { .name = "IB_WR_ATOMIC_FETCH_AND_ADD", .mask = { - [IB_QPT_RC] = WR_ATOMIC_MASK, + [IB_QPT_RC] = WR_ATOMIC_MASK, + [IB_QPT_XRC_INI] = WR_ATOMIC_MASK, }, }, [IB_WR_LSO] = { @@ -71,34 +78,39 @@ struct rxe_wr_opcode_info rxe_wr_opcode_info[] = { [IB_WR_SEND_WITH_INV] = { .name = "IB_WR_SEND_WITH_INV", .mask = { - [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK, - [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK, - [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_RC] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_UC] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_UD] = WR_INLINE_MASK | WR_SEND_MASK, + [IB_QPT_XRC_INI] = WR_INLINE_MASK | WR_SEND_MASK, }, }, [IB_WR_RDMA_READ_WITH_INV] = { .name = "IB_WR_RDMA_READ_WITH_INV", .mask = { - [IB_QPT_RC] = WR_READ_MASK, + [IB_QPT_RC] = WR_READ_MASK, + [IB_QPT_XRC_INI] = WR_READ_MASK, }, }, [IB_WR_LOCAL_INV] = { .name = "IB_WR_LOCAL_INV", .mask = { - [IB_QPT_RC] = WR_LOCAL_OP_MASK, + [IB_QPT_RC] = WR_LOCAL_OP_MASK, + [IB_QPT_XRC_INI] = WR_LOCAL_OP_MASK, }, }, [IB_WR_REG_MR] = { .name = "IB_WR_REG_MR", .mask = { - [IB_QPT_RC] = WR_LOCAL_OP_MASK, + [IB_QPT_RC] = WR_LOCAL_OP_MASK, + [IB_QPT_XRC_INI] = WR_LOCAL_OP_MASK, }, }, [IB_WR_BIND_MW] = { .name = "IB_WR_BIND_MW", .mask = { - [IB_QPT_RC] = WR_LOCAL_OP_MASK, - [IB_QPT_UC] = WR_LOCAL_OP_MASK, + [IB_QPT_RC] = WR_LOCAL_OP_MASK, + [IB_QPT_UC] = WR_LOCAL_OP_MASK, + [IB_QPT_XRC_INI] = WR_LOCAL_OP_MASK, }, }, }; @@ -918,6 +930,327 @@ struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE] = { } }, + /* XRC */ + [IB_OPCODE_XRC_SEND_FIRST] = { + .name = "IB_OPCODE_XRC_SEND_FIRST", + .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK | + RXE_RWR_MASK | RXE_SEND_MASK | RXE_FIRST_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + } + }, + [IB_OPCODE_XRC_SEND_MIDDLE] = { + .name = "IB_OPCODE_XRC_SEND_MIDDLE", + .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK | + RXE_SEND_MASK | RXE_MIDDLE_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + } + }, + [IB_OPCODE_XRC_SEND_LAST] = { + .name = "IB_OPCODE_XRC_SEND_LAST", + .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK | + RXE_COMP_MASK | RXE_SEND_MASK | RXE_LAST_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + } + }, + [IB_OPCODE_XRC_SEND_LAST_WITH_IMMEDIATE] = { + .name = "IB_OPCODE_XRC_SEND_LAST_WITH_IMMEDIATE", + .mask = RXE_XRCETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | + RXE_REQ_MASK | RXE_COMP_MASK | RXE_SEND_MASK | + RXE_LAST_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IMMDT_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_IMMDT] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_IMMDT_BYTES, + } + }, + [IB_OPCODE_XRC_SEND_ONLY] = { + .name = "IB_OPCODE_XRC_SEND_ONLY", + .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK | + RXE_COMP_MASK | RXE_RWR_MASK | RXE_SEND_MASK | + RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + } + }, + [IB_OPCODE_XRC_SEND_ONLY_WITH_IMMEDIATE] = { + .name = "IB_OPCODE_XRC_SEND_ONLY_WITH_IMMEDIATE", + .mask = RXE_XRCETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | + RXE_REQ_MASK | RXE_COMP_MASK | RXE_RWR_MASK | + RXE_SEND_MASK | RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IMMDT_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_IMMDT] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_IMMDT_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_WRITE_FIRST] = { + .name = "IB_OPCODE_XRC_RDMA_WRITE_FIRST", + .mask = RXE_XRCETH_MASK | RXE_RETH_MASK | RXE_PAYLOAD_MASK | + RXE_REQ_MASK | RXE_WRITE_MASK | RXE_FIRST_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_RETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_RETH] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_RETH_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_WRITE_MIDDLE] = { + .name = "IB_OPCODE_XRC_RDMA_WRITE_MIDDLE", + .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK | + RXE_WRITE_MASK | RXE_MIDDLE_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_WRITE_LAST] = { + .name = "IB_OPCODE_XRC_RDMA_WRITE_LAST", + .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK | + RXE_WRITE_MASK | RXE_LAST_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = { + .name = "IB_OPCODE_XRC_RDMA_WRITE_LAST_WITH_IMMEDIATE", + .mask = RXE_XRCETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | + RXE_REQ_MASK | RXE_WRITE_MASK | RXE_COMP_MASK | + RXE_RWR_MASK | RXE_LAST_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IMMDT_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_IMMDT] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_IMMDT_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_WRITE_ONLY] = { + .name = "IB_OPCODE_XRC_RDMA_WRITE_ONLY", + .mask = RXE_XRCETH_MASK | RXE_RETH_MASK | RXE_PAYLOAD_MASK | + RXE_REQ_MASK | RXE_WRITE_MASK | RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_RETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_RETH] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_RETH_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = { + .name = "IB_OPCODE_XRC_RDMA_WRITE_ONLY_WITH_IMMEDIATE", + .mask = RXE_XRCETH_MASK | RXE_RETH_MASK | RXE_IMMDT_MASK | + RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_WRITE_MASK | + RXE_COMP_MASK | RXE_RWR_MASK | RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IMMDT_BYTES + + RXE_RETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_RETH] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_IMMDT] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_RETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_RETH_BYTES + + RXE_IMMDT_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_READ_REQUEST] = { + .name = "IB_OPCODE_XRC_RDMA_READ_REQUEST", + .mask = RXE_XRCETH_MASK | RXE_RETH_MASK | RXE_REQ_MASK | + RXE_READ_MASK | RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_RETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_RETH] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_RETH_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_READ_RESPONSE_FIRST] = { + .name = "IB_OPCODE_XRC_RDMA_READ_RESPONSE_FIRST", + .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK | + RXE_FIRST_MASK, + .length = RXE_BTH_BYTES + RXE_AETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_AETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_AETH_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_READ_RESPONSE_MIDDLE] = { + .name = "IB_OPCODE_XRC_RDMA_READ_RESPONSE_MIDDLE", + .mask = RXE_PAYLOAD_MASK | RXE_ACK_MASK | RXE_MIDDLE_MASK, + .length = RXE_BTH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_PAYLOAD] = RXE_BTH_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_READ_RESPONSE_LAST] = { + .name = "IB_OPCODE_XRC_RDMA_READ_RESPONSE_LAST", + .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK | + RXE_LAST_MASK, + .length = RXE_BTH_BYTES + RXE_AETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_AETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_AETH_BYTES, + } + }, + [IB_OPCODE_XRC_RDMA_READ_RESPONSE_ONLY] = { + .name = "IB_OPCODE_XRC_RDMA_READ_RESPONSE_ONLY", + .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK | + RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_AETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_AETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_AETH_BYTES, + } + }, + [IB_OPCODE_XRC_ACKNOWLEDGE] = { + .name = "IB_OPCODE_XRC_ACKNOWLEDGE", + .mask = RXE_AETH_MASK | RXE_ACK_MASK | RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_AETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_AETH] = RXE_BTH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_AETH_BYTES, + } + }, + [IB_OPCODE_XRC_ATOMIC_ACKNOWLEDGE] = { + .name = "IB_OPCODE_XRC_ATOMIC_ACKNOWLEDGE", + .mask = RXE_AETH_MASK | RXE_ATMACK_MASK | RXE_ACK_MASK | + RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_ATMACK_BYTES + RXE_AETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_AETH] = RXE_BTH_BYTES, + [RXE_ATMACK] = RXE_BTH_BYTES + + RXE_AETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_AETH_BYTES + + RXE_ATMACK_BYTES, + } + }, + [IB_OPCODE_XRC_COMPARE_SWAP] = { + .name = "IB_OPCODE_XRC_COMPARE_SWAP", + .mask = RXE_XRCETH_MASK | RXE_ATMETH_MASK | RXE_REQ_MASK | + RXE_ATOMIC_MASK | RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_ATMETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_ATMETH] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_ATMETH_BYTES, + } + }, + [IB_OPCODE_XRC_FETCH_ADD] = { + .name = "IB_OPCODE_XRC_FETCH_ADD", + .mask = RXE_XRCETH_MASK | RXE_ATMETH_MASK | RXE_REQ_MASK | + RXE_ATOMIC_MASK | RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_ATMETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_ATMETH] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_ATMETH_BYTES, + } + }, + [IB_OPCODE_XRC_SEND_LAST_WITH_INVALIDATE] = { + .name = "IB_OPCODE_XRC_SEND_LAST_WITH_INVALIDATE", + .mask = RXE_XRCETH_MASK | RXE_IETH_MASK | RXE_PAYLOAD_MASK | + RXE_REQ_MASK | RXE_COMP_MASK | RXE_SEND_MASK | + RXE_LAST_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_IETH] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_IETH_BYTES, + } + }, + [IB_OPCODE_XRC_SEND_ONLY_WITH_INVALIDATE] = { + .name = "IB_OPCODE_XRC_SEND_ONLY_INV", + .mask = RXE_XRCETH_MASK | RXE_IETH_MASK | RXE_PAYLOAD_MASK | + RXE_REQ_MASK | RXE_COMP_MASK | RXE_RWR_MASK | + RXE_SEND_MASK | RXE_ONLY_MASK, + .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IETH_BYTES, + .offset = { + [RXE_BTH] = 0, + [RXE_XRCETH] = RXE_BTH_BYTES, + [RXE_IETH] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES, + [RXE_PAYLOAD] = RXE_BTH_BYTES + + RXE_XRCETH_BYTES + + RXE_IETH_BYTES, + } + }, }; static int next_opcode_rc(struct rxe_qp *qp, u32 opcode, int fits) diff --git a/drivers/infiniband/sw/rxe/rxe_opcode.h b/drivers/infiniband/sw/rxe/rxe_opcode.h index d2b6a8232e92..5528a47f0266 100644 --- a/drivers/infiniband/sw/rxe/rxe_opcode.h +++ b/drivers/infiniband/sw/rxe/rxe_opcode.h @@ -30,7 +30,7 @@ enum rxe_wr_mask { struct rxe_wr_opcode_info { char *name; - enum rxe_wr_mask mask[WR_MAX_QPT]; + enum rxe_wr_mask mask[IB_QPT_MAX]; }; extern struct rxe_wr_opcode_info rxe_wr_opcode_info[]; @@ -44,6 +44,7 @@ enum rxe_hdr_type { RXE_ATMETH, RXE_ATMACK, RXE_IETH, + RXE_XRCETH, RXE_RDETH, RXE_DETH, RXE_IMMDT, @@ -61,6 +62,7 @@ enum rxe_hdr_mask { RXE_ATMETH_MASK = BIT(RXE_ATMETH), RXE_ATMACK_MASK = BIT(RXE_ATMACK), RXE_IETH_MASK = BIT(RXE_IETH), + RXE_XRCETH_MASK = BIT(RXE_XRCETH), RXE_RDETH_MASK = BIT(RXE_RDETH), RXE_DETH_MASK = BIT(RXE_DETH), RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD),

[for-next,v2,04/13] RDMA/rxe: Extend opcodes and headers to support xrc

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Patch