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[2603:8081:140c:1a00:c4e7:bfae:90ed:ac81]) by smtp.googlemail.com with ESMTPSA id v17-20020a056808005100b00349a06c581fsm2798557oic.3.2022.09.29.10.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Sep 2022 10:09:10 -0700 (PDT) From: Bob Pearson To: jgg@nvidia.com, zyjzyj2000@gmail.com, linux-rdma@vger.kernel.org Cc: Bob Pearson Subject: [PATCH for-next v2 05/13] RDMA/rxe: Add xrc opcodes to next_opcode() Date: Thu, 29 Sep 2022 12:08:29 -0500 Message-Id: <20220929170836.17838-6-rpearsonhpe@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220929170836.17838-1-rpearsonhpe@gmail.com> References: <20220929170836.17838-1-rpearsonhpe@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org Extend next_opcode() to support xrc operations. Signed-off-by: Bob Pearson --- drivers/infiniband/sw/rxe/rxe_opcode.c | 88 ++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/infiniband/sw/rxe/rxe_opcode.c b/drivers/infiniband/sw/rxe/rxe_opcode.c index 4ae926a37ef8..c2bac0ce444a 100644 --- a/drivers/infiniband/sw/rxe/rxe_opcode.c +++ b/drivers/infiniband/sw/rxe/rxe_opcode.c @@ -1376,6 +1376,91 @@ static int next_opcode_uc(struct rxe_qp *qp, u32 opcode, int fits) return -EINVAL; } +static int next_opcode_xrc(struct rxe_qp *qp, u32 wr_opcode, int fits) +{ + switch (wr_opcode) { + case IB_WR_RDMA_WRITE: + if (qp->req.opcode == IB_OPCODE_XRC_RDMA_WRITE_FIRST || + qp->req.opcode == IB_OPCODE_XRC_RDMA_WRITE_MIDDLE) + return fits ? + IB_OPCODE_XRC_RDMA_WRITE_LAST : + IB_OPCODE_XRC_RDMA_WRITE_MIDDLE; + else + return fits ? + IB_OPCODE_XRC_RDMA_WRITE_ONLY : + IB_OPCODE_XRC_RDMA_WRITE_FIRST; + + case IB_WR_RDMA_WRITE_WITH_IMM: + if (qp->req.opcode == IB_OPCODE_XRC_RDMA_WRITE_FIRST || + qp->req.opcode == IB_OPCODE_XRC_RDMA_WRITE_MIDDLE) + return fits ? + IB_OPCODE_XRC_RDMA_WRITE_LAST_WITH_IMMEDIATE : + IB_OPCODE_XRC_RDMA_WRITE_MIDDLE; + else + return fits ? + IB_OPCODE_XRC_RDMA_WRITE_ONLY_WITH_IMMEDIATE : + IB_OPCODE_XRC_RDMA_WRITE_FIRST; + + case IB_WR_SEND: + if (qp->req.opcode == IB_OPCODE_XRC_SEND_FIRST || + qp->req.opcode == IB_OPCODE_XRC_SEND_MIDDLE) + return fits ? + IB_OPCODE_XRC_SEND_LAST : + IB_OPCODE_XRC_SEND_MIDDLE; + else + return fits ? + IB_OPCODE_XRC_SEND_ONLY : + IB_OPCODE_XRC_SEND_FIRST; + + case IB_WR_SEND_WITH_IMM: + if (qp->req.opcode == IB_OPCODE_XRC_SEND_FIRST || + qp->req.opcode == IB_OPCODE_XRC_SEND_MIDDLE) + return fits ? + IB_OPCODE_XRC_SEND_LAST_WITH_IMMEDIATE : + IB_OPCODE_XRC_SEND_MIDDLE; + else + return fits ? + IB_OPCODE_XRC_SEND_ONLY_WITH_IMMEDIATE : + IB_OPCODE_XRC_SEND_FIRST; + + case IB_WR_RDMA_READ: + return IB_OPCODE_XRC_RDMA_READ_REQUEST; + + case IB_WR_RDMA_READ_WITH_INV: + return IB_OPCODE_XRC_RDMA_READ_REQUEST; + + case IB_WR_ATOMIC_CMP_AND_SWP: + return IB_OPCODE_XRC_COMPARE_SWAP; + + case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: + return -EOPNOTSUPP; + + case IB_WR_ATOMIC_FETCH_AND_ADD: + return IB_OPCODE_XRC_FETCH_ADD; + + case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: + return -EOPNOTSUPP; + + case IB_WR_SEND_WITH_INV: + if (qp->req.opcode == IB_OPCODE_XRC_SEND_FIRST || + qp->req.opcode == IB_OPCODE_XRC_SEND_MIDDLE) + return fits ? + IB_OPCODE_XRC_SEND_LAST_WITH_INVALIDATE : + IB_OPCODE_XRC_SEND_MIDDLE; + else + return fits ? + IB_OPCODE_XRC_SEND_ONLY_WITH_INVALIDATE : + IB_OPCODE_XRC_SEND_FIRST; + + case IB_WR_LOCAL_INV: + case IB_WR_REG_MR: + case IB_WR_BIND_MW: + return wr_opcode; + } + + return -EINVAL; +} + int next_opcode(struct rxe_qp *qp, struct rxe_send_wqe *wqe, u32 opcode) { int fits = (wqe->dma.resid <= qp->mtu); @@ -1387,6 +1472,9 @@ int next_opcode(struct rxe_qp *qp, struct rxe_send_wqe *wqe, u32 opcode) case IB_QPT_UC: return next_opcode_uc(qp, opcode, fits); + case IB_QPT_XRC_INI: + return next_opcode_xrc(qp, opcode, fits); + case IB_QPT_UD: case IB_QPT_GSI: switch (opcode) {