From patchwork Fri Nov 4 23:47:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiraz Saleem X-Patchwork-Id: 13032756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15F79C4332F for ; Fri, 4 Nov 2022 23:48:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229828AbiKDXsI (ORCPT ); Fri, 4 Nov 2022 19:48:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229556AbiKDXsH (ORCPT ); Fri, 4 Nov 2022 19:48:07 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 543092F022 for ; Fri, 4 Nov 2022 16:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667605686; x=1699141686; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VSMIogv+rXfPEF5SwWA5nJeoyEUissXJuzXnt7/C+aI=; b=kBSgyE5cgaFV/7gtit1SFVHZCXha1i73bdk3wFpCc6heeMrTg7CQCqhB 8GQ8bXd0MVO9y3HI2oQfnKYqteJH5ATUu/CY5z1URhemKMa8rP9d88fiL aPIz5ApVl4TIAoCcWIW9XrKqAlRUM9bOxVbdTjIiMfoZ9Vrt7mAOep/St nz+gG+CkOUJq9qnVoLVKmHfFpmFu37HuvuD1BGI+QdXALx+tk29Pgvc4t 4PuKLq5hPHrPpV3ahE8NsztFHXZcP65DTuxrE9PdxA/25AyklJ4fJ3t8H jyxRuJMJM3eQ+Zxa+RJ/++UcKm5MqVmMOHxFy6Ox2dQSdywRMDq6H8Co/ A==; X-IronPort-AV: E=McAfee;i="6500,9779,10521"; a="289826785" X-IronPort-AV: E=Sophos;i="5.96,139,1665471600"; d="scan'208";a="289826785" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2022 16:48:05 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10521"; a="586352316" X-IronPort-AV: E=Sophos;i="5.96,139,1665471600"; d="scan'208";a="586352316" Received: from ssaleem-mobl1.amr.corp.intel.com ([10.255.38.106]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2022 16:48:04 -0700 From: Shiraz Saleem To: jgg@nvidia.com, leon@kernel.org Cc: linux-rdma@vger.kernel.org, Mustafa Ismail , Shiraz Saleem Subject: [PATCH for-next 3/3] RDMA/irdma: Do not request 2-level PBLEs for CQ alloc Date: Fri, 4 Nov 2022 18:47:49 -0500 Message-Id: <20221104234749.1084-4-shiraz.saleem@intel.com> X-Mailer: git-send-email 2.35.2 In-Reply-To: <20221104234749.1084-1-shiraz.saleem@intel.com> References: <20221104234749.1084-1-shiraz.saleem@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Mustafa Ismail When allocating PBLE's for a large CQ, it is possible that a 2-level PBLE is returned which would cause the CQ allocation to fail since 1-level is assumed and checked for. Fix this by requesting a level one PBLE only. Fixes: b48c24c2d710 ("RDMA/irdma: Implement device supported verb APIs") Signed-off-by: Mustafa Ismail Signed-off-by: Shiraz Saleem --- drivers/infiniband/hw/irdma/verbs.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/infiniband/hw/irdma/verbs.c b/drivers/infiniband/hw/irdma/verbs.c index 4f28d99..bfa790c 100644 --- a/drivers/infiniband/hw/irdma/verbs.c +++ b/drivers/infiniband/hw/irdma/verbs.c @@ -2358,9 +2358,10 @@ static bool irdma_check_mr_contiguous(struct irdma_pble_alloc *palloc, * @rf: RDMA PCI function * @iwmr: mr pointer for this memory registration * @use_pbles: flag if to use pble's + * @lvl_1_only: request only level 1 pble if true */ static int irdma_setup_pbles(struct irdma_pci_f *rf, struct irdma_mr *iwmr, - bool use_pbles) + bool use_pbles, bool lvl_1_only) { struct irdma_pbl *iwpbl = &iwmr->iwpbl; struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; @@ -2371,7 +2372,7 @@ static int irdma_setup_pbles(struct irdma_pci_f *rf, struct irdma_mr *iwmr, if (use_pbles) { status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt, - false); + lvl_1_only); if (status) return status; @@ -2414,16 +2415,10 @@ static int irdma_handle_q_mem(struct irdma_device *iwdev, bool ret = true; pg_size = iwmr->page_size; - err = irdma_setup_pbles(iwdev->rf, iwmr, use_pbles); + err = irdma_setup_pbles(iwdev->rf, iwmr, use_pbles, true); if (err) return err; - if (use_pbles && palloc->level != PBLE_LEVEL_1) { - irdma_free_pble(iwdev->rf->pble_rsrc, palloc); - iwpbl->pbl_allocated = false; - return -ENOMEM; - } - if (use_pbles) arr = palloc->level1.addr; @@ -2899,7 +2894,7 @@ static struct ib_mr *irdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 len, case IRDMA_MEMREG_TYPE_MEM: use_pbles = (iwmr->page_cnt != 1); - err = irdma_setup_pbles(iwdev->rf, iwmr, use_pbles); + err = irdma_setup_pbles(iwdev->rf, iwmr, use_pbles, false); if (err) goto error;