Message ID | 20241211134223.389616-13-tariqt@nvidia.com (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show
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Wed, 11 Dec 2024 05:44:18 -0800 From: Tariq Toukan <tariqt@nvidia.com> To: "David S. Miller" <davem@davemloft.net>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Eric Dumazet <edumazet@google.com>, "Andrew Lunn" <andrew+netdev@lunn.ch>, Leon Romanovsky <leonro@nvidia.com> CC: <netdev@vger.kernel.org>, Saeed Mahameed <saeedm@nvidia.com>, Gal Pressman <gal@nvidia.com>, <linux-rdma@vger.kernel.org>, Patrisious Haddad <phaddad@nvidia.com>, Mark Bloch <mbloch@nvidia.com>, Tariq Toukan <tariqt@nvidia.com> Subject: [PATCH net-next 12/12] net/mlx5: fs, Add support for RDMA RX steering over IB link layer Date: Wed, 11 Dec 2024 15:42:23 +0200 Message-ID: <20241211134223.389616-13-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241211134223.389616-1-tariqt@nvidia.com> References: <20241211134223.389616-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: <linux-rdma.vger.kernel.org> List-Subscribe: <mailto:linux-rdma+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-rdma+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3C:EE_|SJ2PR12MB8847:EE_ X-MS-Office365-Filtering-Correlation-Id: f66bae45-7bf1-4b01-1f1e-08dd19e9f46c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: zGCCi8zOI7hruE46o9YugIXDBWAOhEELaX8LcmOS+41XS7fTqWVxuybdOiD95lPIl6GwZDlw5fRHvP4Nk2GKNG7UD0PpU+SvLoQHjSnjdOJJmfHEYZeHXhpGui7clXLycDYhq4BieBdVPnPJ117uLnVb3z5McU7okA5bY0UtR/J84Hp5jzTMJ3WzWMj7dUcbSVx/epAm50vZlmem+SyK2QYkrkRq+R5xjMpAVZPzy5xcwfl4gIM/8+7Qlgv1QwGnVLAqcX489FVgWE9IJB7o02MbjsPvUJVSWH+5qdGC/wtKy6k+3bTQlDP5vj229cZLhwIt0e8iNJ6w57djUxG5Tcpon3xh9mAdNTPJ2Z34/AEp9+eYkogAGayj5dz7CtpogcfzWGRRZJmbcNqTwemQqwm0DEQH19/NuIJsgkSi2ta3lpw+3wu9z4Qpi/oMrKO1ByUEGyRo2pWEd92gsm01C3Pftc2+w+fUAGWdZps9Vfxz6iYnL1+iOnKdpoAwSz8mwaj+wszmV7Mm1kMrItdXriqkNiwA6ZMobg095czk6uMlX1/YeGAWh4n3El+cBbURpfvR5JaS422AQn2YBynXwFiwT/uUZPMCNaeJs7k2cwjLqi1D2fD9f/AIyMEpXSRiWw3RGtW3Yu44/ttB3a2etg59PoWlJQCuGmzw4MM1L1iHaun2Sfk0r6b7w+DGOYX6aER4Ozq6NxjYtgLqWAH1MHWaVTcLzHtdYBLnruk0cC5PMtg4+dtoczIcCw4IB7wizL84FOYtZOt3jilq7DenKVcSP/meQY5ZrghGE1Rq2d8ZPXEvMCSwsR36ok8X+NjBa+POqcku7OVchtaa28SSLW5UOXuYbZ5QM5Nw/7lEJfAMU/wHrE30kS11cHSg2wlqpQEomqHZvAmgHXqPsuUCJSSacFwXscCMmZLR3XhxvMDGmr7N0yLU4Ocz6BYFuJz14Kwl++3E2hqmTNbPkjftyFTs0kjKtWgJAf/N/Y+qNrrg1HuxBwGEbvz0cxEqiPMn57AFSfLXlMplMzcnQRVt2tOTWXLuqiFgRIY+duBJ7qnJszIwVQDJgpIrqTbXl/TxzUMCxO24MZPPfeRauTNEduVwKRjxbvQM8ensGtjqQZsR6tK8dtSWjJ8qc5igMSXHveVjQ8aBIlqCrq6HYwdCz2kMePxHcnsnTrdqI+0LK5fsra0ims2tg4lvpdv6Vjpt1D/9E38jXwgqPByD7xC+WdSLtMj99XSumbLlVHgV2yub1H7kyweyGQWp1XV82SpRz56CDvLavTh338od9eui1fvx2H/bzgU/3qfxStfLT2QsNUbalRflwi0yrCle5v0NO3kS1MDpIb5Ffr4+TiHoi5tMMheihNfkkqRAStF+nx3UCfoFuXdzCE4TC3taDsEea4y86fiiAiigeGYzHhbRjwF0i1u5T9MoJWlwBqWGNTYDFvM2CP+fc0WNcGNtpKTm X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2024 13:44:37.3873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f66bae45-7bf1-4b01-1f1e-08dd19e9f46c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8847 |
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mlx5 misc changes 2024-12-11
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diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c index 6bf0aade69d7..ae20c061e0fb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c @@ -217,7 +217,8 @@ static int mlx5_cmd_update_root_ft(struct mlx5_flow_root_namespace *ns, int err; if ((MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_IB) && - underlay_qpn == 0) + underlay_qpn == 0 && + (ft->type != FS_FT_RDMA_RX && ft->type != FS_FT_RDMA_TX)) return 0; if (ft->type == FS_FT_FDB && diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c index ae1a5705b26d..41b5e98a0495 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -3665,8 +3665,7 @@ int mlx5_fs_core_init(struct mlx5_core_dev *dev) goto err; } - if (MLX5_CAP_FLOWTABLE_RDMA_RX(dev, ft_support) && - MLX5_CAP_FLOWTABLE_RDMA_RX(dev, table_miss_action_domain)) { + if (MLX5_CAP_FLOWTABLE_RDMA_RX(dev, ft_support)) { err = init_rdma_rx_root_ns(steering); if (err) goto err;