Message ID | 20250226114752.104838-5-tariqt@nvidia.com (mailing list archive) |
---|---|
State | New |
Headers | show
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Wed, 26 Feb 2025 03:48:33 -0800 From: Tariq Toukan <tariqt@nvidia.com> To: "David S. Miller" <davem@davemloft.net>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Eric Dumazet <edumazet@google.com>, "Andrew Lunn" <andrew+netdev@lunn.ch> CC: Saeed Mahameed <saeedm@nvidia.com>, Gal Pressman <gal@nvidia.com>, "Leon Romanovsky" <leonro@nvidia.com>, Leon Romanovsky <leon@kernel.org>, "Tariq Toukan" <tariqt@nvidia.com>, <netdev@vger.kernel.org>, <linux-rdma@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Amir Tzin <amirtz@nvidia.com>, Mark Bloch <mbloch@nvidia.com> Subject: [PATCH net-next 4/6] net/mlx5: Lag, Enable Multiport E-Switch offloads on 8 ports LAG Date: Wed, 26 Feb 2025 13:47:50 +0200 Message-ID: <20250226114752.104838-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250226114752.104838-1-tariqt@nvidia.com> References: <20250226114752.104838-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: <linux-rdma.vger.kernel.org> List-Subscribe: <mailto:linux-rdma+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-rdma+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C8:EE_|IA0PR12MB8375:EE_ X-MS-Office365-Filtering-Correlation-Id: a90fcc85-b32a-4500-4d5c-08dd565b8827 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: FW6DmNvfo1ZLbdHeVjRRa0oY15ZTUGGjOfVHC3N4BbTJSS/OwczgCSFkUzaC69WVQlPAscqYQ9/a4MxIr+R74eA8b+R7iXKO8bayAwF8zyUQ58acK4KThvDdTatJuUt5mzzP62jKKGaWVLE2ygXbU52iDkVeS/uCjV9RmV8fDbVEOaPeTw8DhXKo1RN52x3vpsIJ3L8PqPrZeMxGM1mk0VWVUn2aOweN+oBQMocZRKXkWqL+bxI92z5Y0BZM4MoFGedfUxDz6RA3oY7KeSvV8HvIUAtkxq8WQbGYcAEt/H4acWhobglpDMF+FScKlnzp/j5ivKyubjWjA3oOVUJlfHXIGG2r12xV6+W8njb6J8kIPh32ABFM1QgNPvxmaggmqGoQdaHTiAa5W0NLBa7ohd+/ji4KiJvftw9MmDw+sBItPBob6ctOVWUFNQ+HAi589KSBvNeRMl+N9ByUV/AjBTm++hSGNe25OiQbjxVchwjDQDmCp5OBROJh7y4zCF5ZHXH6/klb9qmM4ZBNyoyfm+5KinEkRatx0yOEmk4cwTG9OpM3TQKBneHaqQEgrTxBEoE+udkAaUrJH4JRF+3oCjnDSKdoIsVniZ+fYKfpZ/41tYINbOTS1lPHrUVrrBlQQefAJvSJkSuRuj/bpOFVxW2EkW+Cgt53b8JQJURFiAiNX7HfTEzPQL8mdJFFW9o1ZyYWGRU5yRSjkbYWgcV44ndcyjAmue5zAmTQVR7IEUYSD6L5v/HtEbjjJ47pXYX3BCvgPY8BXnMR7hKZpd+Yp+BtkSCDjfv9rVEqE2eHDUGMr2GJGtgn6dEUyonWopUDlKY1+VPZwmYfPz8UjQ9DVOKP1MGLkoABwiwnYRZG5kn2oQt/eqNfRaiywLWoK9XdPJb/3LD2DtNlZPV1HG/aIQPR/JYk0FoDv6ILGr04/DQ14P2xW6rKu9fENlC7bfZPnvM2dOrAmv9RBv4HSO/AJJv8PE64DC7ovEMLoq32czpllmj31+GMvotD2OXFsn45MJle2f38TRElq5J3BeKF0UJzRGnd/jPMw+irDB4AIwFtJEKrt6G9n+Zyj/WF2xNNzDKSvvybIGNQT8X1pJsTsZygYCGFeQP17Oq8oubA3tb5FTXR4+eJoK+Mf7qNKdp5PXl+GZGPuUe6uKEB/WybHVqviW32YLLOH13eVSLxFYVFAoffr4hRnFKy4qwbEf/BplsDN0Cmp7XfZZS9gromCixvLp39CqST2Gh1hCguLnll15vVLKzVKrFkOGeB52nlaIWTFywe8mrTuWcCZPzzZtZZUkalO8+Zy69S4KGmuQB6XWXCMoJBbBXkR3K4E07vt+3+77R8KbFH5qgqRb7DHy0QOx2Ll392WI57gKlDHF1Y0jp6PX9HqJu4RBVPYHnf4ZMW9S6uRVbAtQMv2MG/Bl1MgaxhQlvaVffBPydkKnQi1YU1VHWHvx5uV2ryeJkelnc87Te/3asV9BT8CqnxfP1moXhJKuVi9goXFAuxuTk= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 11:48:48.1517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a90fcc85-b32a-4500-4d5c-08dd565b8827 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8375 |
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mlx5 misc enhancements 2025-02-26
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diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c index ffac0bd6c895..cbde54324059 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -65,7 +65,6 @@ static int mlx5_mpesw_metadata_set(struct mlx5_lag *ldev) return err; } -#define MLX5_LAG_MPESW_OFFLOADS_SUPPORTED_PORTS 4 static int enable_mpesw(struct mlx5_lag *ldev) { int idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); @@ -77,9 +76,6 @@ static int enable_mpesw(struct mlx5_lag *ldev) return -EINVAL; dev0 = ldev->pf[idx].dev; - if (ldev->ports > MLX5_LAG_MPESW_OFFLOADS_SUPPORTED_PORTS) - return -EOPNOTSUPP; - if (mlx5_eswitch_mode(dev0) != MLX5_ESWITCH_OFFLOADS || !MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table) || !MLX5_CAP_GEN(dev0, create_lag_when_not_master_up) ||