From patchwork Thu Jun 29 14:17:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 9817119 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 181B760365 for ; Thu, 29 Jun 2017 14:18:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A6A9280CF for ; Thu, 29 Jun 2017 14:18:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F2CFB285D9; Thu, 29 Jun 2017 14:18:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 82A85280CF for ; Thu, 29 Jun 2017 14:18:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753408AbdF2OSj (ORCPT ); Thu, 29 Jun 2017 10:18:39 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51676 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753401AbdF2OS1 (ORCPT ); Thu, 29 Jun 2017 10:18:27 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5542B60879; Thu, 29 Jun 2017 14:18:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498745886; bh=65uaRDGtBleoHfJoOyz1ksw3tLvKuE3nMsQK0DoXIlI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OziXP5uwgJXlSb4YxQmYrtkSMHHJQ5m3B35b01LhQdgfQfYMaVtOWgDHZkLG/5319 iYy7UQ8vUvMxK9WeDEwhpds92fNbcAS+PefSKhBIONzV0ZVy1UY8Vh7I31noTP8upP QxHgojB6fOwJk6E/FIhF2HgOQCxu9ZgpoMIeArF4= Received: from srichara-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sricharan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B2BF760B7F; Thu, 29 Jun 2017 14:18:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498745885; bh=65uaRDGtBleoHfJoOyz1ksw3tLvKuE3nMsQK0DoXIlI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SVs21otIeKJXXfds0Z/W03oVzgoh716XozjgI2tRwQiXJZAncyi+Qe4mWvGDTH9cy 1wk0pRn+R1Gt/glNuR3/Rk+iF5+QHmV8bs0/YK6QRkHOUk3o4jZReBSw6KgHf7FgOv LXD6SGNULPfPxyUSJ6SO/PERM1PwDAJosQ44VAsk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B2BF760B7F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Cc: sricharan@codeaurora.org Subject: [PATCH 3/3] dt-binding: remoteproc: Add the bindings required for Q6 - WCSS core Date: Thu, 29 Jun 2017 19:47:41 +0530 Message-Id: <1498745861-20531-4-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498745861-20531-1-git-send-email-sricharan@codeaurora.org> References: <1498745861-20531-1-git-send-email-sricharan@codeaurora.org> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP IPQ8074 has an integrated Q6V5 Hexagon dsp - Lithium Wlan (WCSS) core. This patch adds the required bindings to load, boot, shutdown that remoteproc subsystem. Signed-off-by: Sricharan R --- .../bindings/remoteproc/qcom,q6v5-wcss.txt | 139 +++++++++++++++++++++ 1 file changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,q6v5-wcss.txt diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5-wcss.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5-wcss.txt new file mode 100644 index 0000000..f664c26 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5-wcss.txt @@ -0,0 +1,139 @@ +Qualcomm Hexagon (Q6) - WCSS Peripheral Image Loader + +This document defines the binding for a component that loads and boots firmware +on the integrated Qualcomm Hexagon - WCSS core. + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,q6v5-wcss-pil", +- reg: + Usage: required + Value type: + Definition: must specify the base address and size of the qdsp6 and + mpm (msm power manager) register blocks. + +- reg-names: + Usage: required + Value type: + Definition: must be "q6" and "mpm" + +- interrupts-extended: + Usage: required + Value type: + Definition: must list the watchdog, fatal IRQs ready, handover and + stop-ack IRQs + +- interrupt-names: + Usage: required + Value type: + Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" + +- clocks: + Usage: required + Value type: + Definition: references to the axim-q6, axim2-q6, axi-wcss, + ahb-q6, ahbs-q6, ahb-wcss, ahbs-wcss, sysnoc and mem. + to be held on behalf of the booting of the Hexagon and WCSS + core. These are the interface, bus, mem clocks required for + the Q6 and WCSS cores. + +- clock-names: + Usage: required + Value type: + Definition: must be "axim-q6", "axim2-q6", "axi-wcss", "ahb-q6", + "ahbs-q6", "ahb-wcss", "ahbs-wcss", "sysnoc", "mem" + +- resets: + Usage: required + Value type: + Definition: reference to the reset-controller for the Q6-WCSS sub-system + +- reset-names: + Usage: required + Value type: + Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" + +- qcom,smem-states: + Usage: required + Value type: + Definition: reference to the smem state for requesting the Hexagon to + shut down + +- qcom,smem-state-names: + Usage: required + Value type: + Definition: must be "stop" + +- qcom,halt-regs: + Usage: required + Value type: + Definition: a phandle reference to a syscon representing TCSR followed + by the three offsets within syscon for q6, wcss and tcsr global + halt registers. + += SUBNODES: +The Hexagon node must contain a subnode, named "q6" representing +the memory region used by the Hexagon firmware. The sub-node must contain: + +- memory-region: + Usage: required + Value type: + Definition: reference to the reserved-memory for the Q6 firmware region + += EXAMPLE +The following example describes the resources needed to boot control the +Hexagon, as it is found on IPQ8074 boards. + + q6v5_wcss: q6v5_wcss@CD00000 { + compatible = "q6v5-wcss-pil"; + reg = <0xCD00000 0x4040>, + <0x4ab000 0x20>; + reg-names = "q6", + "mpm"; + interrupts-extended = <&intc 0 325 1>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "handover", + "stop-ack"; + clocks = <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>, + <&gcc GCC_WCSS_AHB_S_CLK>, + <&gcc GCC_WCSS_ECAHB_CLK>, + <&gcc GCC_Q6_AHB_CLK>, + <&gcc GCC_Q6_AHB_S_CLK>, + <&gcc GCC_WCSS_AXI_M_CLK>, + <&gcc GCC_MEM_NOC_Q6_AXI_CLK>, + <&gcc GCC_Q6_AXIM_CLK>, + <&gcc GCC_Q6_AXIM2_CLK>; + clock-names = "sysnoc", + "ahb-wcss", + "ahbs-wcss", + "ahb-q6", + "ahbs-q6", + "axi-wcss", + "memnoc", + "axim-q6", + "axim2-q6"; + + resets = <&gcc GCC_WCSSAON_RESET>, + <&gcc GCC_WCSS_BCR>, + <&gcc GCC_WCSS_Q6_BCR>; + + reset-names = "wcss_aon_reset", + "wcss_reset", + "wcss_q6_reset"; + + qcom,halt-regs = <&tcsr_mutex_block 0x0 0xA000 0xD000>; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + q6 { + memory-region = <&q6_region>; + }; + };