From patchwork Wed Aug 30 15:13:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 9929987 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 904DD60309 for ; Wed, 30 Aug 2017 15:15:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 816B0286BE for ; Wed, 30 Aug 2017 15:15:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 762D3286BF; Wed, 30 Aug 2017 15:15:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DB7E2286BA for ; Wed, 30 Aug 2017 15:15:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751784AbdH3POT (ORCPT ); Wed, 30 Aug 2017 11:14:19 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:48876 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751740AbdH3POP (ORCPT ); Wed, 30 Aug 2017 11:14:15 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8F193607B6; Wed, 30 Aug 2017 15:14:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1504106054; bh=cBy1ZyOo+huvlnHPLRnMEaKbfDteoI4WW8V+wtczIF4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f1R02u7YrvVQS3qvGPzXD2dBmYEsj9lDEOXTh86Ew+WDMiyr3lVRdBwbAk/vUKWBC hu8mscKU4GhLISd6Zm3MA5IlIzHwSNVaHopWww/HuqC3l1Ms90Pe5Y5TOhiCna5F2Y Bu7LrBP0fdrCQ7ReTDIMzg0XbzYB5BlfzRUz4i+8= Received: from srichara-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sricharan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F3ACD607E8; Wed, 30 Aug 2017 15:14:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1504106052; bh=cBy1ZyOo+huvlnHPLRnMEaKbfDteoI4WW8V+wtczIF4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q8YtVUReFAP9YhrH7Gk9pF6eLeIgIDViwmZ8A4tJc7b1cQ+ct4uut5dCVlqpxojrn J77FU8PSSbE4l9llFJXTBo6v54eZS1Xf9MnEgR/c+CfTTozFT/BGfVg2OuU9fg/JE8 g5n449/mJS/xvXjuwNLv2rC0YMNEUSY5CMxqcCaA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F3ACD607E8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: bjorn.andersson@linaro.org, ohad@wizery.com, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Cc: sricharan@codeaurora.org Subject: [PATCH v2 4/6] remoteproc: qcom: Split the head and tail of the q6v5-pil rproc start function Date: Wed, 30 Aug 2017 20:43:42 +0530 Message-Id: <1504106024-23569-5-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1504106024-23569-1-git-send-email-sricharan@codeaurora.org> References: <1504106024-23569-1-git-send-email-sricharan@codeaurora.org> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Most of the q6v5-pil start function is same for the q6v5-wcss rproc that will be added later. So split and move out the common pieces so that the same code can be reused. Signed-off-by: Sricharan R --- drivers/remoteproc/qcom_q6v5_pil.c | 165 +++++++++++++++++++++---------------- 1 file changed, 94 insertions(+), 71 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c index afe5092..232134c 100644 --- a/drivers/remoteproc/qcom_q6v5_pil.c +++ b/drivers/remoteproc/qcom_q6v5_pil.c @@ -407,74 +407,113 @@ static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms) return val; } -static int q6v5proc_reset(struct q6v5 *qproc) +static int q6v5_reset(struct q6v5 *qproc) { u32 val; int ret; int i; + /* Assert resets, stop core */ + val = readl(qproc->reg_base + QDSP6SS_RESET_REG); + val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; + writel(val, qproc->reg_base + QDSP6SS_RESET_REG); - if (qproc->version == MSS_MSM8996) { - /* Override the ACC value if required */ - writel(QDSP6SS_ACC_OVERRIDE_VAL, - qproc->reg_base + QDSP6SS_STRAP_ACC); + /* BHS require xo cbcr to be enabled */ + val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); + val |= 0x1; + writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); - /* Assert resets, stop core */ - val = readl(qproc->reg_base + QDSP6SS_RESET_REG); - val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; - writel(val, qproc->reg_base + QDSP6SS_RESET_REG); + /* Read CLKOFF bit to go low indicating CLK is enabled */ + ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, + val, !(val & BIT(31)), 1, + HALT_CHECK_MAX_LOOPS); + if (ret) { + dev_err(qproc->dev, + "xo cbcr enabling timed out (rc:%d)\n", ret); + return ret; + } - /* BHS require xo cbcr to be enabled */ - val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); - val |= 0x1; - writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); + /* Enable power block headswitch and wait for it to stabilize */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= QDSP6v56_BHS_ON; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + udelay(1); - /* Read CLKOFF bit to go low indicating CLK is enabled */ - ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, - val, !(val & BIT(31)), 1, HALT_CHECK_MAX_LOOPS); - if (ret) { - dev_err(qproc->dev, - "xo cbcr enabling timed out (rc:%d)\n", ret); - return ret; - } - /* Enable power block headswitch and wait for it to stabilize */ - val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val |= QDSP6v56_BHS_ON; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + /* Put LDO in bypass mode */ + val |= QDSP6v56_LDO_BYP; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Deassert QDSP6 compiler memory clamp */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val &= ~QDSP6v56_CLAMP_QMC_MEM; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Deassert memory peripheral sleep and L2 memory standby */ + val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Turn on L1, L2, ETB and JU memories 1 at a time */ + val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); + for (i = 19; i >= 0; i--) { + val |= BIT(i); + writel(val, qproc->reg_base + QDSP6SS_MEM_PWR_CTL); + /* + * Read back value to ensure the write is done then + * wait for 1us for both memory peripheral and data + * array to turn on. + */ + val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); udelay(1); + } - /* Put LDO in bypass mode */ - val |= QDSP6v56_LDO_BYP; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + /* Remove word line clamp */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val &= ~QDSP6v56_CLAMP_WL; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - /* Deassert QDSP6 compiler memory clamp */ - val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val &= ~QDSP6v56_CLAMP_QMC_MEM; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + return 0; +} - /* Deassert memory peripheral sleep and L2 memory standby */ - val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); +static void q6v5_reset_rest(struct q6v5 *qproc) +{ + u32 val; - /* Turn on L1, L2, ETB and JU memories 1 at a time */ - val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); - for (i = 19; i >= 0; i--) { - val |= BIT(i); - writel(val, qproc->reg_base + - QDSP6SS_MEM_PWR_CTL); - /* - * Read back value to ensure the write is done then - * wait for 1us for both memory peripheral and data - * array to turn on. - */ - val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); - udelay(1); - } - /* Remove word line clamp */ - val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val &= ~QDSP6v56_CLAMP_WL; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Remove IO clamp */ + val &= ~Q6SS_CLAMP_IO; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Bring core out of reset */ + val = readl(qproc->reg_base + QDSP6SS_RESET_REG); + val &= ~Q6SS_CORE_ARES; + writel(val, qproc->reg_base + QDSP6SS_RESET_REG); + + /* Turn on core clock */ + val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); + val |= Q6SS_CLK_ENABLE; + writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); + + /* Start core execution */ + val = readl(qproc->reg_base + QDSP6SS_RESET_REG); + val &= ~Q6SS_STOP_CORE; + writel(val, qproc->reg_base + QDSP6SS_RESET_REG); +} + +static int q6v5proc_reset(struct q6v5 *qproc) +{ + u32 val; + int ret; + + if (qproc->version == MSS_MSM8996) { + /* Override the ACC value if required */ + writel(QDSP6SS_ACC_OVERRIDE_VAL, + qproc->reg_base + QDSP6SS_STRAP_ACC); + + ret = q6v5_reset(qproc); + if (ret) + return ret; } else { /* Assert resets, stop core */ val = readl(qproc->reg_base + QDSP6SS_RESET_REG); @@ -502,24 +541,8 @@ static int q6v5proc_reset(struct q6v5 *qproc) val |= Q6SS_L2DATA_SLP_NRET_N_0; writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); } - /* Remove IO clamp */ - val &= ~Q6SS_CLAMP_IO; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - - /* Bring core out of reset */ - val = readl(qproc->reg_base + QDSP6SS_RESET_REG); - val &= ~Q6SS_CORE_ARES; - writel(val, qproc->reg_base + QDSP6SS_RESET_REG); - /* Turn on core clock */ - val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); - val |= Q6SS_CLK_ENABLE; - writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); - - /* Start core execution */ - val = readl(qproc->reg_base + QDSP6SS_RESET_REG); - val &= ~Q6SS_STOP_CORE; - writel(val, qproc->reg_base + QDSP6SS_RESET_REG); + q6v5_reset_rest(qproc); /* Wait for PBL status */ ret = q6v5_rmb_pbl_wait(qproc, 1000);