From patchwork Tue Oct 9 13:05:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Govind Singh X-Patchwork-Id: 10632453 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B390A13AD for ; Tue, 9 Oct 2018 13:06:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9365228BB4 for ; Tue, 9 Oct 2018 13:06:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8509428DB7; Tue, 9 Oct 2018 13:06:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22B4528BB4 for ; Tue, 9 Oct 2018 13:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726984AbeJIUXH (ORCPT ); Tue, 9 Oct 2018 16:23:07 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60776 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726496AbeJIUXH (ORCPT ); Tue, 9 Oct 2018 16:23:07 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0047760392; Tue, 9 Oct 2018 13:06:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1539090375; bh=T1jYb0LHy0nalrz7FeFQc8MsNtRsRV2f78lT/8NvuUw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B9gs9Ynkyyq11EsWq1/HYHC4d0PpBg2DSJNNYK6q2qUONXlWHR7DCthVYMTI9+GVF wa1i1M0eun70oPv0GJcgw8mz7EDsv1JiodXR/KBzsFQzrYdQ7cQWErg6GlTMfoqoxV 35dAqgcW8vxDWzo2frbsj20mxVtVfFQ9k0ZKZRWQ= Received: from svishnoi-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: govinds@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DA54C60BFE; Tue, 9 Oct 2018 13:06:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1539090374; bh=T1jYb0LHy0nalrz7FeFQc8MsNtRsRV2f78lT/8NvuUw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VgcvpbaFogLYMQam4N39oestMtaWziXzvggJmrNFo3qo+rgOlvkaRjrNX8CC25OVZ Zn4Jqb4/KG/GuNOtJcBL/F3I46emFclZAVeZwhgea4JMe516j/TgtidxWba9dygeqw KBKa2seSxdxl2bOaH1xrDzFW/9DPiHObJtpmwRLs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DA54C60BFE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=govinds@codeaurora.org From: Govind Singh To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, sricharan@codeaurora.org, sibis@codeaurora.org, linux-arm-msm@vger.kernel.org, andy.gross@linaro.org, david.brown@linaro.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: Govind Singh Subject: [PATCH 2/6] clk: qcom: Add WCSS gcc clock control for QCS404 Date: Tue, 9 Oct 2018 18:35:53 +0530 Message-Id: <1539090357-20853-3-git-send-email-govinds@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1539090357-20853-1-git-send-email-govinds@codeaurora.org> References: <1539090357-20853-1-git-send-email-govinds@codeaurora.org> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the WCSS QDSP gcc clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required gcc clocks to bring the subsystem out of reset. Signed-off-by: Govind Singh --- drivers/clk/qcom/gcc-qcs404.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 6d1387e..bcbfe19 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -2505,6 +2505,34 @@ enum { }, }; +static struct clk_branch gcc_ahbs_cbcr_clk = { + .halt_reg = 0x1e004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ahb_cbcr_clk", + .ops = &clk_branch2_ops, + .flags = CLK_IGNORE_UNUSED, + }, + }, +}; + +static struct clk_branch gcc_axim_cbcr_clk = { + .halt_reg = 0x1e008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_axim_cbcr_clk", + .ops = &clk_branch2_ops, + .flags = CLK_IGNORE_UNUSED, + }, + }, +}; + static struct clk_regmap *gcc_qcs404_clocks[] = { [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, [BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr, @@ -2642,6 +2670,9 @@ enum { [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, + [GCC_WCSS_Q6_AHB_CBCR_CLK] = NULL, + [GCC_WCSS_Q6_AXIM_CBCR_CLK] = NULL, + }; static const struct qcom_reset_map gcc_qcs404_resets[] = { @@ -2659,6 +2690,7 @@ enum { [GCC_PCIE_0_LINK_DOWN_BCR] = {0x3E038}, [GCC_PCIEPHY_0_PHY_BCR] = {0x3E03C}, [GCC_EMAC_BCR] = {0x4E000}, + [GCC_WDSP_RESTART] = {0x19000}, }; static const struct regmap_config gcc_qcs404_regmap_config = { @@ -2669,7 +2701,7 @@ enum { .fast_io = true, }; -static const struct qcom_cc_desc gcc_qcs404_desc = { +static struct qcom_cc_desc gcc_qcs404_desc = { .config = &gcc_qcs404_regmap_config, .clks = gcc_qcs404_clocks, .num_clks = ARRAY_SIZE(gcc_qcs404_clocks), @@ -2702,6 +2734,11 @@ static int gcc_qcs404_probe(struct platform_device *pdev) clk_prepare_enable(apss_ahb_clk_src.clkr.hw.clk); clk_prepare_enable(gpll0_ao_out_main.clkr.hw.clk); + if (of_property_read_bool(pdev->dev.of_node, "qcom,wcss-protected")) { + gcc_qcs404_clocks[GCC_WCSS_Q6_AHB_CBCR_CLK] = &gcc_ahbs_cbcr_clk.clkr; + gcc_qcs404_clocks[GCC_WCSS_Q6_AXIM_CBCR_CLK] = &gcc_axim_cbcr_clk.clkr; + } + return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap); }