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Thu, 8 Nov 2018 09:06:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726653AbeKHSju (ORCPT ); Thu, 8 Nov 2018 13:39:50 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:50551 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726359AbeKHSjs (ORCPT ); Thu, 8 Nov 2018 13:39:48 -0500 Received: by mail-wm1-f68.google.com with SMTP id 124-v6so453279wmw.0 for ; Thu, 08 Nov 2018 01:05:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jRCk5lNBlPCD7GwKBzaRehaZeMJbLJXp2+/KqxIsFvY=; b=PRCeYAKI1JDWmpfIB+fVwGmz1XhZopfERjhSMfAfj3b0fJndvCuqDwWV6yzY1OtbFK 0W//QSrqpdNuwU+HsEqHP9pCgjJsWcXAJay1v5nz294M2/jrG/HVUvpKpy0mHF2fRCeq M0S3gqspgYb9Z1kMebrHkdqa0KPLAVfu6Vbzg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jRCk5lNBlPCD7GwKBzaRehaZeMJbLJXp2+/KqxIsFvY=; b=X4BSafc+0QcXNbCZRwnQhTE4H0ub5vq6wlMz2NmgNIj8weWHANx6Y7WkKqKvlIuEzO cNUDoQRGUJZREI009FR70ZC/2eztUAkpEdqXpjC0bK/N2SW9HryYWSMdEYkX3tUFjemJ 0C3hwqpP8xrFQ8evoiuy6O8yGWJovP+yoStOXyIiC9EkGyMMXqA+atvVmcxDtjJpWbGA 9Wr3OVQbdvrxum4wpDWdO3eb90ELZmi1GgQIyOEciWGkIWXLN0rEaBoILlQDCvKCXIOV IK9IEfEVUASjZRC/5YcW+VCgYhmjDUYuh7/GdtsrQACF9ugqh+VpR+OLSZ1kn7WpURjg ZDfQ== X-Gm-Message-State: AGRZ1gKqeguMVrYIBT+GKbQNM71Mq/iibk/7/5yNkWYnPOUvfVye4kig YPGII+HWScMjsYF9gj4T6Ff0lw== X-Google-Smtp-Source: AJdET5fTS06uzWUmAt5qrVnJNaHoFWBuVdlyggZVVgrWQkFkHAKhOM7cxVKHTm9+CO0iMvwifDK43A== X-Received: by 2002:a1c:b4c1:: with SMTP id d184-v6mr412831wmf.143.1541667916129; Thu, 08 Nov 2018 01:05:16 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1094:149:440c:9368:8cda:a020]) by smtp.gmail.com with ESMTPSA id l140-v6sm6974469wmb.24.2018.11.08.01.05.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Nov 2018 01:05:15 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v2 1/4] dt-bindings: hwlock: Document STM32 hwspinlock bindings Date: Thu, 8 Nov 2018 10:04:59 +0100 Message-Id: <20181108090502.14543-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181108090502.14543-1-benjamin.gaignard@st.com> References: <20181108090502.14543-1-benjamin.gaignard@st.com> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add bindings for STM32 hardware spinlock device Signed-off-by: Benjamin Gaignard --- version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt new file mode 100644 index 000000000000..6e933b218574 --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -0,0 +1,23 @@ +STM32 Hardware Spinlock Device Binding +------------------------------------- + +Required properties : +- compatible : should be "st,stm32-hwspinlock". +- reg : the register address of hwspinlock. +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. +- clock-names : Must contain "hwspinlock". +- clocks : Must contain a phandle entry for the clock in clock-names, see the + common clock bindings. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + };