From patchwork Fri Oct 2 23:42:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11814765 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 68EBF139A for ; Fri, 2 Oct 2020 23:43:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 49C3E206A2 for ; Fri, 2 Oct 2020 23:43:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="C529dgdN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725497AbgJBXnL (ORCPT ); Fri, 2 Oct 2020 19:43:11 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:49268 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725835AbgJBXnK (ORCPT ); Fri, 2 Oct 2020 19:43:10 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 092Nh6AD076824; Fri, 2 Oct 2020 18:43:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1601682186; bh=aEtPlK33RiIjfQGTy5W9aHKWcGq5l0p9CTrcxdBmdZU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=C529dgdNGvryZdVOGSQZeulia34vQMCysdD8R96GNTVqzecnT7gwBIOr9dh5xnbha 6WZ1klVcw+AWC9xX2ACh74/Zumy0W+NcVjY+FiU8PQwYuG3vcjaGG1NoJh7N3/78Jt pdlrIhajL1k8GsAB1DOS++LZnAZ4gOYv36LbE70s= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 092Nh6EQ041859 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Oct 2020 18:43:06 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 2 Oct 2020 18:43:05 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 2 Oct 2020 18:43:05 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 092Nh5e4069681; Fri, 2 Oct 2020 18:43:05 -0500 Received: from localhost ([10.250.37.92]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 092Nh5g0113355; Fri, 2 Oct 2020 18:43:05 -0500 From: Suman Anna To: Bjorn Andersson , Rob Herring , Mathieu Poirier CC: Lokesh Vutla , , , , , Suman Anna Subject: [PATCH v5 3/4] remoteproc: k3-r5: Initialize TCM memories for ECC Date: Fri, 2 Oct 2020 18:42:33 -0500 Message-ID: <20201002234234.20704-4-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201002234234.20704-1-s-anna@ti.com> References: <20201002234234.20704-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org The R5F processors on K3 SoCs all have two TCMs (ATCM and BTCM) that support 32-bit ECC. The TCMs are typically loaded with some boot-up code to initialize the R5 MPUs to further execute code out of DDR. The ECC for the TCMs is enabled by default on K3 SoCs due to internal default tie-off values, but the TCM memories are not initialized on device power up. Any read access without the corresponding TCM memory location initialized will generate an ECC error, and any such access from a A72 or A53 core will trigger a SError. So, zero initialize both the TCM memories before loading any firmware onto a R5F in remoteproc mode. Any R5F booted from U-Boot/SPL would require a similar initialization in the bootloader. Note that both the TCMs are initialized unconditionally as the TCM enable config bits only manage the access and visibility from R5. Signed-off-by: Suman Anna Reviewed-by: Mathieu Poirier --- v5: No changes v4: No changes v3: https://patchwork.kernel.org/patch/11679335/ - No code changes, picked up tags v2: https://patchwork.kernel.org/patch/11632989/ v1: https://patchwork.kernel.org/patch/11456371/ drivers/remoteproc/ti_k3_r5_remoteproc.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5_remoteproc.c b/drivers/remoteproc/ti_k3_r5_remoteproc.c index 15e52ea67bbe..a6b395ab47b6 100644 --- a/drivers/remoteproc/ti_k3_r5_remoteproc.c +++ b/drivers/remoteproc/ti_k3_r5_remoteproc.c @@ -362,11 +362,24 @@ static int k3_r5_rproc_prepare(struct rproc *rproc) ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP) ? k3_r5_lockstep_release(cluster) : k3_r5_split_release(core); - if (ret) + if (ret) { dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n", ret); + return ret; + } - return ret; + /* + * Zero out both TCMs unconditionally (access from v8 Arm core is not + * affected by ATCM & BTCM enable configuration values) so that ECC + * can be effective on all TCM addresses. + */ + dev_dbg(dev, "zeroing out ATCM memory\n"); + memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size); + + dev_dbg(dev, "zeroing out BTCM memory\n"); + memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size); + + return 0; } /*