Message ID | 20211123062050.1442712-3-tanmay.shah@xilinx.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Add Xilinx RPU subsystem support | expand |
On Mon, Nov 22, 2021 at 10:20:46PM -0800, Tanmay Shah wrote: > RPU subsystem can be configured in cluster-mode or split mode. > Also each r5 core has separate power domains. > > Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com> > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 28dccb891a53..f4fb98ccb1b5 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -654,6 +654,23 @@ qspi: spi@ff0f0000 { > power-domains = <&zynqmp_firmware PD_QSPI>; > }; > > + r5fss: r5fss@ff9a0000 { > + compatible = "xlnx,zynqmp-r5fss"; > + xlnx,cluster-mode = <1>; > + > + reg = <0x0 0Xff9a0000 0x0 0x228>; This line is giving me an obvious checkpatch warning. Please make sure you run checkpatch.pl before sending out a patchset. > + > + r5f_core0: r5f-0 { > + compatible = "xlnx,zynqmp-r5f"; > + power-domains = <&zynqmp_firmware PD_RPU_0>; > + }; > + > + r5f_core1: r5f-1 { > + compatible = "xlnx,zynqmp-r5f"; > + power-domains = <&zynqmp_firmware PD_RPU_1>; > + }; > + }; > + > psgtr: phy@fd400000 { > compatible = "xlnx,zynqmp-psgtr-v1.1"; > status = "disabled"; > -- > 2.25.1 >
Hi Mathieu, Thanks for reviews. Please find my responses inline. On 11/29/21 11:28 PM, Mathieu Poirier wrote: > On Mon, Nov 22, 2021 at 10:20:46PM -0800, Tanmay Shah wrote: >> RPU subsystem can be configured in cluster-mode or split mode. >> Also each r5 core has separate power domains. >> >> Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com> >> --- >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 17 +++++++++++++++++ >> 1 file changed, 17 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> index 28dccb891a53..f4fb98ccb1b5 100644 >> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> @@ -654,6 +654,23 @@ qspi: spi@ff0f0000 { >> power-domains = <&zynqmp_firmware PD_QSPI>; >> }; >> >> + r5fss: r5fss@ff9a0000 { >> + compatible = "xlnx,zynqmp-r5fss"; >> + xlnx,cluster-mode = <1>; >> + >> + reg = <0x0 0Xff9a0000 0x0 0x228>; > This line is giving me an obvious checkpatch warning. Please make sure you run > checkpatch.pl before sending out a patchset. > I ran checkpatch.pl on patches that contains .c files and .h files and I had fixed lot of style related warnings using checkpatch.pl. However, I had misunderstanding that checkpatch.pl should not be used for patches with .yaml and .dtsi files. So I skipped it for bindings patch and dtsi patch. Thanks for correcting me here. I will make sure to run checkpatch.pl for all patches from here. Also, I will fix this error in next revision. >> + >> + r5f_core0: r5f-0 { >> + compatible = "xlnx,zynqmp-r5f"; >> + power-domains = <&zynqmp_firmware PD_RPU_0>; >> + }; >> + >> + r5f_core1: r5f-1 { >> + compatible = "xlnx,zynqmp-r5f"; >> + power-domains = <&zynqmp_firmware PD_RPU_1>; >> + }; >> + }; >> + >> psgtr: phy@fd400000 { >> compatible = "xlnx,zynqmp-psgtr-v1.1"; >> status = "disabled"; >> -- >> 2.25.1 >>
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 28dccb891a53..f4fb98ccb1b5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -654,6 +654,23 @@ qspi: spi@ff0f0000 { power-domains = <&zynqmp_firmware PD_QSPI>; }; + r5fss: r5fss@ff9a0000 { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + reg = <0x0 0Xff9a0000 0x0 0x228>; + + r5f_core0: r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_0>; + }; + + r5f_core1: r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_1>; + }; + }; + psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled";
RPU subsystem can be configured in cluster-mode or split mode. Also each r5 core has separate power domains. Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com> --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)