From patchwork Wed Jun 1 11:21:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12866752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B744AC43219 for ; Wed, 1 Jun 2022 11:22:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352547AbiFALWS (ORCPT ); Wed, 1 Jun 2022 07:22:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244616AbiFALWO (ORCPT ); Wed, 1 Jun 2022 07:22:14 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E7044199F; Wed, 1 Jun 2022 04:22:12 -0700 (PDT) X-UUID: 5a77fbfa935d4a73a6275b136ae3b29a-20220601 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:7d44fd19-a9a8-4e18-9fb8-283159bfc891,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:2a19b09,CLOUDID:a1648f14-f88c-475e-badf-d9ee54230b8f,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 5a77fbfa935d4a73a6275b136ae3b29a-20220601 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 53229942; Wed, 01 Jun 2022 19:22:06 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 1 Jun 2022 19:22:04 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 1 Jun 2022 19:22:04 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Lee Jones , Benson Leung , Guenter Roeck , Daisuke Nojiri , Sebastian Reichel , "Dustin L. Howett" , Tzung-Bi Shih , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra , Brian Norris CC: , , , , , , , Subject: [PATCH v1 04/15] remoteproc: mediatek: Add SCP core 1 register definitions Date: Wed, 1 Jun 2022 19:21:50 +0800 Message-ID: <20220601112201.15510-5-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220601112201.15510-1-tinghan.shen@mediatek.com> References: <20220601112201.15510-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Add MT8195 SCP core 1 related register definitions. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 73e8adf00de3..2eadb0e696a1 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_SCP2SPM_IPC_CLR 0x4094 #define MT8192_GIPC_IN_SET 0x4098 #define MT8192_HOST_IPC_INT_BIT BIT(0) +#define MT8195_HOST_IPC_INT_BIT BIT(4) #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 @@ -60,6 +61,26 @@ #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) +#define MT8195_CPU1_SRAM_PD 0x1084 +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 +#define MT8195_CORE1_SW_RSTN_SET 0x20004 +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 +#define MT8195_CORE1_WDT_CFG 0x20034 + +#define MT8195_SEC_CTRL 0x85000 +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 +#define MT8195_L2TCM_OFFSET 0x850d0 +#define SCP_SRAM_REMAP_LOW 0 +#define SCP_SRAM_REMAP_HIGH 1 +#define SCP_SRAM_REMAP_OFFSET 2 +#define SCP_SRAM_REMAP_SIZE 3 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288