From patchwork Wed Jun 8 08:35:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70F06CCA487 for ; Wed, 8 Jun 2022 09:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234501AbiFHJP6 (ORCPT ); Wed, 8 Jun 2022 05:15:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235090AbiFHJOa (ORCPT ); Wed, 8 Jun 2022 05:14:30 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 566EF1D81A8; Wed, 8 Jun 2022 01:36:10 -0700 (PDT) X-UUID: d6de6976b3ba4611902d7eb46160c50d-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:fdf95160-d3b8-466b-9dce-cb9891f2b2ea,OB:30,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:fdf95160-d3b8-466b-9dce-cb9891f2b2ea,OB:30,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:3f2515e5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: d6de6976b3ba4611902d7eb46160c50d-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1726167700; Wed, 08 Jun 2022 16:36:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 6/9] remoteproc: mediatek: Add SCP core 1 SRAM offset Date: Wed, 8 Jun 2022 16:35:50 +0800 Message-ID: <20220608083553.8697-7-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Because SCP core 0 and core 1 both boot from address 0 and have the same viewpoint of memory, HW has a set of registers, "SRAM offset", to add offset to accessed address for SCP core 1 to solve this problem. The "SRAM offset" configuration is composed by specifying a range and an offset. The value of range is from the viewpoint of SCP core 1. When SCP core 1 accessing addresses in the configured range, SCP bus adds an offset to shift the destination on SCP SRAM. This shift is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 731a8094c373..b8a4db581179 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -505,6 +505,27 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) static int mt8195_scp_dual_before_load(struct mtk_scp *scp) { u32 sec_ctrl; + struct device *dev = scp->dev; + struct device_node *main_np; + struct platform_device *main_pdev; + struct mtk_scp *scp_core0; + + /* Get sram start address from SCP core 0 */ + main_np = of_parse_phandle(dev->of_node, "mediatek,scp-core", 0); + if (!main_np) { + dev_warn(dev, "Invalid SCP main core phandle\n"); + return -EINVAL; + } + + main_pdev = of_find_device_by_node(main_np); + of_node_put(main_np); + + if (!main_pdev) { + dev_err(dev, "Cannot find SCP core 0 device\n"); + return -ENODEV; + } + scp_core0 = platform_get_drvdata(main_pdev); + put_device(&main_pdev->dev); scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); @@ -514,6 +535,27 @@ static int mt8195_scp_dual_before_load(struct mtk_scp *scp) /* enable MPU for all memory regions */ writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + /* The value of SRAM offset range is from the viewpoint of SCP core 1. + * This configuration adds an offset on SCP bus when SCP core 1 accesses SCP SRAM + * to solve the SCP core 0 and core 1 both fetch the 1st instruction from the same + * SRAM address. + * + * Because SCP core 0 and core 1 both boot from address 0, this must be configured + * before boot SCP core 1. + * + * Configure the range of SRAM addresses will be added offset. + */ + writel(0, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW); + writel(scp->sram_size, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH); + + /* configure the offset value */ + writel(scp->sram_phys - scp_core0->sram_phys, scp->reg_base + MT8195_L2TCM_OFFSET); + + /* enable adding sram offset when fetching instruction and data */ + sec_ctrl = readl(scp->reg_base + MT8195_SEC_CTRL); + sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D; + writel(sec_ctrl, scp->reg_base + MT8195_SEC_CTRL); + return 0; }