From patchwork Wed Feb 15 04:12:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 13141276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48149C64ED6 for ; Wed, 15 Feb 2023 04:13:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232544AbjBOENU (ORCPT ); Tue, 14 Feb 2023 23:13:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231174AbjBOENL (ORCPT ); Tue, 14 Feb 2023 23:13:11 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A46F824C8E; Tue, 14 Feb 2023 20:13:07 -0800 (PST) X-UUID: 0881b100ace711ed945fc101203acc17-20230215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6HhKK4J2H3bm5JiXJDgPozBzQTQbRGkWm2dygfVNSZ0=; b=DtaBOIVmKMNeM3Y4vauIQSSS4kBUuyGbmZtkGF1sUS+ma9BY0xFURoPlVgwEthIBjjm5PIvqeKKxXq7DJvOoR3LJ+3wHCHAM0tCVJJ4R1GF6KY+Ll+XmDheYfG+ISpfccM40irHR4jyYJf7KTuyOuBhCXFKQiVyjdTr9Cbbv7Y0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:af47e1e1-deb5-4ffa-999b-9b7ffa39fa2b,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:885ddb2,CLOUDID:f57609f3-ddba-41c3-91d9-10eeade8eac7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: 0881b100ace711ed945fc101203acc17-20230215 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 257835529; Wed, 15 Feb 2023 12:12:59 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 15 Feb 2023 12:12:58 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 15 Feb 2023 12:12:58 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v7 04/12] remoteproc: mediatek: Add SCP core 1 register definitions Date: Wed, 15 Feb 2023 12:12:49 +0800 Message-ID: <20230215041257.14548-5-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230215041257.14548-1-tinghan.shen@mediatek.com> References: <20230215041257.14548-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Add MT8195 SCP core 1 related register definitions. Signed-off-by: Tinghan Shen Reviewed-by: Mathieu Poirier Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index ea6fa1100a00..3778894c96f3 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_SCP2SPM_IPC_CLR 0x4094 #define MT8192_GIPC_IN_SET 0x4098 #define MT8192_HOST_IPC_INT_BIT BIT(0) +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 @@ -56,6 +57,26 @@ #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) +#define MT8195_CPU1_SRAM_PD 0x1084 +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 +#define MT8195_CORE1_SW_RSTN_SET 0x20004 +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 +#define MT8195_CORE1_WDT_CFG 0x20034 + +#define MT8195_SEC_CTRL 0x85000 +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 +#define MT8195_L2TCM_OFFSET 0x850d0 +#define SCP_SRAM_REMAP_LOW 0 +#define SCP_SRAM_REMAP_HIGH 1 +#define SCP_SRAM_REMAP_OFFSET 2 +#define SCP_SRAM_REMAP_SIZE 3 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288