From patchwork Fri Mar 31 15:46:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud POULIQUEN X-Patchwork-Id: 13196127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21AF2C77B62 for ; Fri, 31 Mar 2023 15:47:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233269AbjCaPrf (ORCPT ); Fri, 31 Mar 2023 11:47:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232953AbjCaPrc (ORCPT ); Fri, 31 Mar 2023 11:47:32 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8342130F0; Fri, 31 Mar 2023 08:47:31 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32VEudSD029004; Fri, 31 Mar 2023 17:47:17 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=4+o068s17JcYDuxCnjJGX6YoOMN2Cbu4UUex4Zuq5vA=; b=EP8ac7L8ocq6z10FwNtr/nOIcZPaSjRWsUAQFRGk/BsyBHDSB54tzjCDgpxjxYtcTf+b t7WS7vZA04tAUBvyKe+WPwDQ7/fcqFJ5Eqa3JTa8o3iY9H1n21FcLlFzUHiCl+elef5V +RZ4CKBSgjJCLaPWfAKHOb0gkvNDDtrxIVfCfPzSzBGQW0o4i1FfWJSjS956q89/ZGF6 PUt0wRAN5gVi0/ahHZj/EeYe73oQmhjykcAbfPTU0bIqQC8uTB/DcROSosN/e6uTyOjP shLRGveizHZdNmnkTzGcQ3g9uXFA6Mt1p1dYnFYgiVNWuGafzWPMzEaI/i3mqvx9zWlc rg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3pnwt09tmp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 31 Mar 2023 17:47:17 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B8F03100038; Fri, 31 Mar 2023 17:47:16 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B2C03222CAF; Fri, 31 Mar 2023 17:47:16 +0200 (CEST) Received: from localhost (10.201.21.178) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Fri, 31 Mar 2023 17:47:15 +0200 From: Arnaud Pouliquen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Alexandre Torgue CC: , , , , Subject: [PATCH 2/5] ARM: dts: stm32: Remove the st,syscfg-tz property Date: Fri, 31 Mar 2023 17:46:48 +0200 Message-ID: <20230331154651.3107173-3-arnaud.pouliquen@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230331154651.3107173-1-arnaud.pouliquen@foss.st.com> References: <20230331154651.3107173-1-arnaud.pouliquen@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.178] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-31_07,2023-03-31_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Since the introduction of the SCMI server for the management of the MCU hold boot in OPTEE, management of the hold boot by smc call is deprecated. Clean the st,syscfg-tz which allows to determine if the trust zone is enable. Signed-off-by: Arnaud Pouliquen --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 4e437d3f2ed6..25626797db94 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1820,8 +1820,8 @@ m4_rproc: m4@10000000 { <0x30000000 0x40000>, <0x38000000 0x10000>; resets = <&rcc MCU_R>; + reset-names = "mcu_rst"; st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;