From patchwork Mon Jun 10 18:06:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13692351 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FF5314B96C; Mon, 10 Jun 2024 18:06:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718042794; cv=none; b=kiD5e8WHk8Omjf4Gcvu4ENnLfTlDQITEdTXFklFvUGDnXUDWwOzSw8NgGC6P5YLT0m7WXix7VUEVJl0q22p89ZQCVsv4MID1Lx/Jv7EupSlHwapwOCKSqs3zfqHTqEAxyRBjti1lEOhAN9JkNC+syQwY2pHbclk+/Apb+++hLiY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718042794; c=relaxed/simple; bh=j+wJNqq6LN1l9QOUCTlh+E//BNnt6ndNLoX5XFvnuHQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Sq6sc0etQq6n3x34wNUqd5lyEcoMLN+UOqRwBCOipYCzy0o+tXIVlSIT8h1yhKx08Z0HEMgTeLSf836u++7zzTpOfKAgfinGriSM3YcrAGaAJicNXJiyrDz2VZxBjokP/Cue+gO3MBi+WHHQZCrDJE2RDJfLe9+Glkbrp7tdIOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=rLhIN45e; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="rLhIN45e" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45AI6KfQ063716; Mon, 10 Jun 2024 13:06:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718042780; bh=QbLyDp54gEuMeUkswIcMc++rcLqlSvQ+Z1iN7qMEziM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rLhIN45ekWGvsWwAZ1UBkHHv5s81UCeDbZ4qycHQaWNMBPt+Dx3qwJq83n96VlwZ8 zjHnsYGo5CHWL4h6ot1CVlIzo+wEQUiOCMn6dbItIB7aR24S3JAWuK87vgZe8NsqPn AnL0wXLs/pgSOBgmdz4uM6CrQXIthIfnlA9MaQts= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45AI6KjD022920 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Jun 2024 13:06:20 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 10 Jun 2024 13:06:20 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 10 Jun 2024 13:06:20 -0500 Received: from lelvsmtp5.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45AI6Gtl056905; Mon, 10 Jun 2024 13:06:19 -0500 From: Andrew Davis To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Philipp Zabel , Hari Nagalla CC: , , , , Andrew Davis Subject: [PATCH v10 6/8] arm64: dts: ti: k3-am642-sk: Add M4F remoteproc node Date: Mon, 10 Jun 2024 13:06:13 -0500 Message-ID: <20240610180615.313622-7-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240610180615.313622-1-afd@ti.com> References: <20240610180615.313622-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 From: Hari Nagalla The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. The first region is used as a DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each rproc device. The M4F processor does not have an MMU, and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Hari Nagalla Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 5b028b3a3192f..727d467ed2c1d 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -99,6 +99,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { no-map; }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; @@ -666,6 +678,13 @@ &main_r5fss1_core1 { <&main_r5fss1_core1_memory_region>; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J3 */