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Mon, 15 Jul 2024 20:41:16 -0500 From: Tanmay Shah To: , CC: , , Tanmay Shah Subject: [PATCH v2] remoteproc: xlnx: add sram support Date: Mon, 15 Jul 2024 18:39:54 -0700 Message-ID: <20240716013953.1715134-1-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: tanmay.shah@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|CH3PR12MB8236:EE_ X-MS-Office365-Filtering-Correlation-Id: cb9076cf-03fb-4b6d-c7b0-08dca53868ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: PLtabaXYJVzSqWHj7RhqnA1JqAULJK5I+ujALcdX1UGq4KDzy1Ryef0LWPX41wAGrFfyCvWSJ/Qzr+GkmefwPr1yzCTfI4aQaQ2I4X2YSAOaNkQsLP0Rg72QNQAR2Ig5TwANYwqEBt06AaXy35G+9IDeROL7lWLta0lai0yUyzrM2zuZJmeU4Ta41tskAK+vuhaOXAa2aqpbfO06/UoLwgJH5ctRjsZ44gIBg007v92VTf3cmiVvkMwqoCB68WUUglEA/jl+fiHdt4aFftP7xVAfkkIDWVXJ402PE8EL0R9q0Z8uYZWg22t0NHccDEyYc/uvSWpd4MJITOEytOrdN2FsWSUtZs8kOBZSnz5b1ghTowWAFcWZheRpEwadgSP8STRUtwppZZrKxrwdoNzdJz4L7UhCyInuec1+Qi6UGhwYtvLMCn5S5nos5U8/IqbwdXk9essSweFvuH5lNKyW1QYPNRoiDLwQuc5JXtb3p3B8b5ESGDwhSsfIqR6eTvAIHCt3gj6aagj4oAd2Ln2dbDZbqJj08m3XHw/MUQ/DXX/f2C2PNbDpYxLpWE/ht1CF4BaIizS6hTncFWR+7JEAs1d3ioM9D+KK4qeU6yf9he4syxLgtsN8QVYXwdwjMVzObGi2iNFG+X6yzo+OCE97LB3AHfX8miysJafcZznJZgtdzBlBVOoNPsjcaQ+Kg7bpsIGRwQMC7kiJ199wA4nHmol+C744IZptx2iMhytmsLmrjQmTPlgpKjVatGrPAnDnbFcWYenYRKMBY2xRIOQz0SOmQoY/M5seSWx5Iv0KweAE6AKtR8TeNFjKKzXjJ9HgTM++64JSf9IDN+FDc4RgCfobnKAEbmPgO7+Xe0f5VRXTMf/kSuVQ1H1h1gs3S0Z1GyQgwpf5suF8Yx3sIc/NTIUXQALUYufqiWTzSU7FynX6TeernoIRiChfahUuIvWQVb9qpQjU/7IfnyrQyiW/3Tl4dIfLp53Sd3VHMo61JqsKKccQspcscbtOVf/cTYj5eIzxn8VI0GBACPwZkJFXeo6UqHrgYaAOcRxG9H6nLOxRx04gZ35D9ezztkoUYwDZh8y/pvqO6UgXPCHcpKYtjvDo/BbjJz23lZilX7m3w+E+58CMrwonxtYIXeqExauMTROHyPWnXawknO1oYitbkWSNAFWpOLVsyaH9R68g+/VRKyPt+0BjXxE4503KR0CPjIJE3zIoqvI3lTNPJzpC+Kl+NJ+QEdWo7U6+EeTJFLBeBq8wJGQtQfjQv4i+h1lAY1+upYJxyIvkMJImXOC1hIrmxWyloA/2WKpsdyB/82VqeApsSko4yjectd6IjTcVAIKHfX9atjb53WwGxtzuHIH+/AYefIezQ5LgsakWoxDRjhz49gDj2FW4anYEitHVjJJHAZ1isCR6LpC285PhgG47133Lc+7NV2SMpH0UA0m2HWyOpDCpntMroLSgrkVR X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2024 01:41:27.3545 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb9076cf-03fb-4b6d-c7b0-08dca53868ca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8236 AMD-Xilinx zynqmp platform contains on-chip sram memory (OCM). R5 cores can access OCM and access is faster than DDR memory but slower than TCM memories available. Sram region can have optional multiple power-domains. Platform management firmware is responsible to operate these power-domains. Signed-off-by: Tanmay Shah --- Changes in v2: - Expand commit message with power-domains related information. drivers/remoteproc/xlnx_r5_remoteproc.c | 131 ++++++++++++++++++++++++ 1 file changed, 131 insertions(+) base-commit: d87dbfd31796f810ed777aee4919f211b4a6c7fb diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c index 596f3ffb8935..52ddd42b09e0 100644 --- a/drivers/remoteproc/xlnx_r5_remoteproc.c +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -56,6 +56,17 @@ struct mem_bank_data { char *bank_name; }; +/** + * struct zynqmp_sram_bank - sram bank description + * + * @sram_res: sram address region information + * @da: device address of sram + */ +struct zynqmp_sram_bank { + struct resource sram_res; + u32 da; +}; + /** * struct mbox_info * @@ -120,6 +131,8 @@ static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = { * struct zynqmp_r5_core * * @rsc_tbl_va: resource table virtual address + * @sram: Array of sram memories assigned to this core + * @num_sram: number of sram for this core * @dev: device of RPU instance * @np: device node of RPU instance * @tcm_bank_count: number TCM banks accessible to this RPU @@ -131,6 +144,8 @@ static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = { */ struct zynqmp_r5_core { void __iomem *rsc_tbl_va; + struct zynqmp_sram_bank **sram; + int num_sram; struct device *dev; struct device_node *np; int tcm_bank_count; @@ -494,6 +509,40 @@ static int add_mem_regions_carveout(struct rproc *rproc) return 0; } +static int add_sram_carveouts(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + struct rproc_mem_entry *rproc_mem; + struct zynqmp_sram_bank *sram; + dma_addr_t dma_addr; + size_t len; + int da, i; + + for (i = 0; i < r5_core->num_sram; i++) { + sram = r5_core->sram[i]; + + dma_addr = (dma_addr_t)sram->sram_res.start; + len = resource_size(&sram->sram_res); + da = sram->da; + + /* Register associated reserved memory regions */ + rproc_mem = rproc_mem_entry_init(&rproc->dev, NULL, + (dma_addr_t)dma_addr, + len, da, + zynqmp_r5_mem_region_map, + zynqmp_r5_mem_region_unmap, + sram->sram_res.name); + + rproc_add_carveout(rproc, rproc_mem); + rproc_coredump_add_segment(rproc, da, len); + + dev_dbg(&rproc->dev, "sram carveout %s addr=%llx, da=0x%x, size=0x%lx", + sram->sram_res.name, dma_addr, da, len); + } + + return 0; +} + /* * tcm_mem_unmap() * @rproc: single R5 core's corresponding rproc instance @@ -669,6 +718,12 @@ static int zynqmp_r5_rproc_prepare(struct rproc *rproc) return ret; } + ret = add_sram_carveouts(rproc); + if (ret) { + dev_err(&rproc->dev, "failed to get sram carveout %d\n", ret); + return ret; + } + return 0; } @@ -881,6 +936,78 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev) return ERR_PTR(ret); } +static int zynqmp_r5_get_sram_banks(struct zynqmp_r5_core *r5_core) +{ + struct zynqmp_sram_bank **sram, *sram_data; + struct device_node *np = r5_core->np; + struct device *dev = r5_core->dev; + struct device_node *sram_np; + int num_sram, i, ret; + u64 abs_addr, size; + + /* "sram" is optional proprty. Do not fail, if unavailable. */ + if (!of_find_property(r5_core->np, "sram", NULL)) + return 0; + + num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle)); + if (num_sram <= 0) { + dev_err(dev, "Invalid sram property, ret = %d\n", + num_sram); + return -EINVAL; + } + + sram = devm_kcalloc(dev, num_sram, + sizeof(struct zynqmp_sram_bank *), GFP_KERNEL); + if (!sram) + return -ENOMEM; + + for (i = 0; i < num_sram; i++) { + sram_data = devm_kzalloc(dev, sizeof(struct zynqmp_sram_bank), + GFP_KERNEL); + if (!sram_data) + return -ENOMEM; + + sram_np = of_parse_phandle(np, "sram", i); + if (!sram_np) { + dev_err(dev, "failed to get sram %d phandle\n", i); + return -EINVAL; + } + + if (!of_device_is_available(sram_np)) { + of_node_put(sram_np); + dev_err(dev, "sram device not available\n"); + return -EINVAL; + } + + ret = of_address_to_resource(sram_np, 0, &sram_data->sram_res); + of_node_put(sram_np); + if (ret) { + dev_err(dev, "addr to res failed\n"); + return ret; + } + + /* Get SRAM device address */ + ret = of_property_read_reg(sram_np, i, &abs_addr, &size); + if (ret) { + dev_err(dev, "failed to get reg property\n"); + return ret; + } + + sram_data->da = (u32)abs_addr; + + sram[i] = sram_data; + + dev_dbg(dev, "sram %d: name=%s, addr=0x%llx, da=0x%x, size=0x%llx\n", + i, sram[i]->sram_res.name, sram[i]->sram_res.start, + sram[i]->da, resource_size(&sram[i]->sram_res)); + } + + r5_core->sram = sram; + r5_core->num_sram = num_sram; + + return 0; +} + static int zynqmp_r5_get_tcm_node_from_dt(struct zynqmp_r5_cluster *cluster) { int i, j, tcm_bank_count, ret, tcm_pd_idx, pd_count; @@ -1095,6 +1222,10 @@ static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster, return ret; } } + + ret = zynqmp_r5_get_sram_banks(r5_core); + if (ret) + return ret; } return 0;