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Fri, 30 Aug 2024 12:38:35 -0500 From: Tanmay Shah To: , CC: , , Tanmay Shah Subject: [PATCH v5] remoteproc: xlnx: add sram support Date: Fri, 30 Aug 2024 10:37:36 -0700 Message-ID: <20240830173735.279432-1-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: tanmay.shah@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000000A0:EE_|DS0PR12MB6488:EE_ X-MS-Office365-Filtering-Correlation-Id: efec7b8a-b6c6-4bf0-4243-08dcc91a9492 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: u9XefQV9QY99hYBBGjgzqun1+0Yzopl/2W2ttRN/HOfnphbIc5W621K9ocvsH8tAEHVxXpkSTbbKcDF/4zWhdu6L74MGiri787H5utDJpvXWxJ5JfOAtQUWePDHAijqAs8wYEFKKYBSkW79OQWaWLfRL+itGFJR7tNNVUj/rrFGrzmKzelrkU2SISuJHe3hkd3VBnZqtSv+NHjj+/qIJGms3DuTTJqUO1mWfmItHSbvFI5xFScVLwTfFGWW5JnLGvBNrZLGChL5i5tv6rqXPuRAIeQyo3vdvQXf87bhzU5sOKMWe5vfLZyuKCcA+lr7shasY7dARpcXuqt8UDv3rISs78HRH6NbvXsX4GK9yn3Cx9qAto0OCjMGcI1x8gf5sr0EvivyiVKshPOJitaibgalveY4r7Y6p+b2va2Zoy+NassiQPpNzKiQwK99yChPu11E6HNgkezhldOmTSL6oEi+0DTs/WQx+AKOrzC0KP1kGse+bngyaPzXCvY7EUupb70bkvPJV3+wzlby5s0Na9k4kKp9iWgws9OkmWPIJ9mdWFh4abdnh3Fbkw8lnpdv7Je4DPqnSdJ8NOrJbRgFyVJhSO1ZgqzpLYChN+YnRxZ8pE21GsdKvQsqoddLQJ4BYKsbDYMbIf7nVqtETvLEWMcrTZTnzrH1LnTlLg8N2nnkFR83DBZyBOUU6t6zMbF+PIZ4/sui31DnYtRA4b6Seg1DY74XJ+dQjNVRS7q9Mif5VNVj1rz8CRNB6q1PgH0vR7CeICE75PRloU9xK3hgzoEe3rafvA9xv8EjhIggppiJau4eC8AalOiHaM3P9uBFZqumIgDQH5p6pFCqVr5ne2/Q7IashNmrrGS1RqfUC4ZLxAnll6L2arV98Z8bC23K5GR1nFRN4xAyh1jd0I+CNGHDfWd4g0VoUUSg5VhekXVLljlGZnTvgekSrMhMIB96kK3zWE+xteof4TdVEewvpd/utqnEOj+qfSs8g8zssl2rE7jDjWXPT7iCgvC7Wc2Jw+d3GCiOI+gaDzTCpzNsK4GxIzeerPUci3XoKT3V5YvxJp19SlHA149QbRIuNLP5oxCGR7DGPHmhxX3ttPlZno4cbEQ8zZ12pAVCANsaoG/iGnnVkZRjKDrWP20zq47gDBeV0aYQxgmF0xyQ7MZ1NMzxKPjFPZnahef3hZR407OwYM5N1GftXLfhO7XVjCjh/hO0J898WiMwe4PnVhmEeSt//EhDjsOUDUtSR/xE13WTjQt0nJBQ/gtVXdl6m+6qY+5/8Evx0FiW2FG7rITyUV1w8j11uUXWP48uYN7P1zawkLmIIyv8IK9DhTQrLzzpDT2b6eMLOr/TyJbAFM7VlkjRDAVsn6qNVN/pUv7TLorjnfMrj6MzeCS6OLtHB6gpNYYK66e/Tkfn6Kswj1w1ll1PzJRlM7D6dPbZT/ArKk5ZqKwi+NlwaInzzPypgyGUG X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Aug 2024 17:38:37.5432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efec7b8a-b6c6-4bf0-4243-08dcc91a9492 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000000A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6488 AMD-Xilinx zynqmp platform contains on-chip sram memory (OCM). R5 cores can access OCM and access is faster than DDR memory but slower than TCM memories available. Sram region can have optional multiple power-domains. Platform management firmware is responsible to operate these power-domains. Signed-off-by: Tanmay Shah --- Changes in v5: - remoteproc: xlnx: remove genpool use for OCM sram Changes in v4: - Free previously allocalted genpool if adding carveouts fail for any sram. - add comment about sram size used in creating carveouts. Changes in v3: - make @sram an array rather than an array of pointers - fix of_node_put usage to maintain proper refcount of node - s/proprty/property - Use gen pool framework for mapping sram address space. Changes in v2: - Expand commit message with power-domains related information. drivers/remoteproc/xlnx_r5_remoteproc.c | 135 ++++++++++++++++++++++++ 1 file changed, 135 insertions(+) base-commit: 057e5c17e29fe67fae4c2786d558c31fd3b106ba diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c index 2cea97c746fd..af4e0e53dc9d 100644 --- a/drivers/remoteproc/xlnx_r5_remoteproc.c +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -56,6 +56,17 @@ struct mem_bank_data { char *bank_name; }; +/** + * struct zynqmp_sram_bank - sram bank description + * + * @sram_res: sram address region information + * @da: device address of sram + */ +struct zynqmp_sram_bank { + struct resource sram_res; + u32 da; +}; + /** * struct mbox_info * @@ -120,6 +131,8 @@ static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = { * struct zynqmp_r5_core * * @rsc_tbl_va: resource table virtual address + * @sram: Array of sram memories assigned to this core + * @num_sram: number of sram for this core * @dev: device of RPU instance * @np: device node of RPU instance * @tcm_bank_count: number TCM banks accessible to this RPU @@ -131,6 +144,8 @@ static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = { */ struct zynqmp_r5_core { void __iomem *rsc_tbl_va; + struct zynqmp_sram_bank *sram; + int num_sram; struct device *dev; struct device_node *np; int tcm_bank_count; @@ -494,6 +509,45 @@ static int add_mem_regions_carveout(struct rproc *rproc) return 0; } +static int add_sram_carveouts(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + struct rproc_mem_entry *rproc_mem; + struct zynqmp_sram_bank *sram; + dma_addr_t dma_addr; + size_t len; + int da, i; + + for (i = 0; i < r5_core->num_sram; i++) { + sram = &r5_core->sram[i]; + + dma_addr = (dma_addr_t)sram->sram_res.start; + + len = resource_size(&sram->sram_res); + da = sram->da; + + rproc_mem = rproc_mem_entry_init(&rproc->dev, NULL, + (dma_addr_t)dma_addr, + len, da, + zynqmp_r5_mem_region_map, + zynqmp_r5_mem_region_unmap, + sram->sram_res.name); + if (!rproc_mem) { + dev_err(&rproc->dev, "failed to add sram %s da=0x%x, size=0x%lx", + sram->sram_res.name, da, len); + return -ENOMEM; + } + + rproc_add_carveout(rproc, rproc_mem); + rproc_coredump_add_segment(rproc, da, len); + + dev_dbg(&rproc->dev, "sram carveout %s addr=%llx, da=0x%x, size=0x%lx", + sram->sram_res.name, dma_addr, da, len); + } + + return 0; +} + /* * tcm_mem_unmap() * @rproc: single R5 core's corresponding rproc instance @@ -669,6 +723,12 @@ static int zynqmp_r5_rproc_prepare(struct rproc *rproc) return ret; } + ret = add_sram_carveouts(rproc); + if (ret) { + dev_err(&rproc->dev, "failed to get sram carveout %d\n", ret); + return ret; + } + return 0; } @@ -881,6 +941,77 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev) return ERR_PTR(ret); } +static int zynqmp_r5_get_sram_banks(struct zynqmp_r5_core *r5_core) +{ + struct device_node *np = r5_core->np; + struct device *dev = r5_core->dev; + struct zynqmp_sram_bank *sram; + struct device_node *sram_np; + int num_sram, i, ret; + u64 abs_addr, size; + + /* "sram" is optional property. Do not fail, if unavailable. */ + if (!of_property_present(r5_core->np, "sram")) + return 0; + + num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle)); + if (num_sram <= 0) { + dev_err(dev, "Invalid sram property, ret = %d\n", + num_sram); + return -EINVAL; + } + + sram = devm_kcalloc(dev, num_sram, + sizeof(struct zynqmp_sram_bank), GFP_KERNEL); + if (!sram) + return -ENOMEM; + + for (i = 0; i < num_sram; i++) { + sram_np = of_parse_phandle(np, "sram", i); + if (!sram_np) { + dev_err(dev, "failed to get sram %d phandle\n", i); + return -EINVAL; + } + + if (!of_device_is_available(sram_np)) { + dev_err(dev, "sram device not available\n"); + ret = -EINVAL; + goto fail_sram_get; + } + + ret = of_address_to_resource(sram_np, 0, &sram[i].sram_res); + if (ret) { + dev_err(dev, "addr to res failed\n"); + goto fail_sram_get; + } + + /* Get SRAM device address */ + ret = of_property_read_reg(sram_np, i, &abs_addr, &size); + if (ret) { + dev_err(dev, "failed to get reg property\n"); + goto fail_sram_get; + } + + sram[i].da = (u32)abs_addr; + + of_node_put(sram_np); + + dev_dbg(dev, "sram %d: name=%s, addr=0x%llx, da=0x%x, size=0x%llx\n", + i, sram[i].sram_res.name, sram[i].sram_res.start, + sram[i].da, resource_size(&sram[i].sram_res)); + } + + r5_core->sram = sram; + r5_core->num_sram = num_sram; + + return 0; + +fail_sram_get: + of_node_put(sram_np); + + return ret; +} + static int zynqmp_r5_get_tcm_node_from_dt(struct zynqmp_r5_cluster *cluster) { int i, j, tcm_bank_count, ret, tcm_pd_idx, pd_count; @@ -1095,6 +1226,10 @@ static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster, return ret; } } + + ret = zynqmp_r5_get_sram_banks(r5_core); + if (ret) + return ret; } return 0;