From patchwork Thu Jan 31 09:40:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10790217 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C23417E9 for ; Thu, 31 Jan 2019 09:40:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DCBC2FE93 for ; Thu, 31 Jan 2019 09:40:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 622EF3065D; Thu, 31 Jan 2019 09:40:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75C142FE93 for ; Thu, 31 Jan 2019 09:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727501AbfAaJk1 (ORCPT ); Thu, 31 Jan 2019 04:40:27 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:59163 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725963AbfAaJk1 (ORCPT ); Thu, 31 Jan 2019 04:40:27 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id CADD025B82E; Thu, 31 Jan 2019 20:40:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1548927625; bh=ZAkEB8WJ4sKnPg9dfuptA0/2TP8l1z/+rVpmGXQ7c+g=; h=From:To:Cc:Subject:Date:From; b=q24NTZrLumOG2U3RN6MtD1um4hHg8CQTAO6ZmVoYc72GnWde4GYiB8xtsuMR2KWiy PfhQ1/zqeR8juhsvzfvRWrn1zMoh32Qg8kMHPqLd6xb2tUs93wOYBffT0OESQ7Z4P3 6kK4HhRzDnZqQqWWuyNKsRw6AyHZvcK05xZbjB6s= Received: by reginn.horms.nl (Postfix, from userid 7100) id DBAD1940600; Thu, 31 Jan 2019 10:40:22 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Simon Horman Subject: [PATCH v3 0/5] clk: renesas: r8a77990: Add Z2 clock Date: Thu, 31 Jan 2019 10:40:16 +0100 Message-Id: <20190131094021.3092-1-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, this series adds the R-Car E3 (r8a77990) Z2 clock as a clock with both a fixed and variable divisor with a parent of PLL0. In order to do so this series: 1. Parameterise Z and Z2 clock fixed divisor in shared Gen-3 CPG driver code to allow fixed divisors other than 2 - the E3 Z2 clock has a fixed divisor of 4 2. Parameterise offset of Z and Z2 clock controll bits - the offsets on E3 differ to other R-Car Gen 3 SoCs 3. Support Z and Z2 clocks with high frequency parents. The parent of the E3 Z2 clock, PLL0, is 4.8GHz and thus when expressed in HZ must be treated as a 64bit value. 4. Actually add the E3 Z2 clock As a follow-up, as per reading the documentation, the RZ/G2E (r8a774c0) Z2 clock is added. Changes since v2 ---------------- * Parameterise control bit offset rather than using a quirk * Revised RZ/G2E patch - I was confused and updating the file for the wrong part number Testing Overview ---------------- This patchset has not been tested on RZ/G2E. This patchset has been tested on Ebisu-4D/E3 with "[PATCH/RFT] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices" applied on top of renesas-devel-20190128-v5.0-rc4. This allowed CPUFreq to be successfully exercised, showing scaling of the Z2 clock as per the results below. This patchset was also tested for regressions Salvator-X/M3-W ES1.0. As per the results below CPUFreq was used to show that with these patches applied Z and Z2 clocks still scale as expected. Patches List by Author ---------------------- Simon Horman (3): clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents [RFT] clk: renesas: r8a774c0: Add Z2 clock Takeshi Kihara (2): clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r8a77990: Add Z2 clock drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a7796-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +- drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + drivers/clk/renesas/rcar-gen3-cpg.c | 26 ++++++++++++-------------- drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ 8 files changed, 27 insertions(+), 21 deletions(-)