[v2,0/3] SoC identification support for RZ/G2L

Message ID	20210609163717.3083-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
Headers	show Return-Path: <linux-renesas-soc-owner@kernel.org> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Rob Herring <robh+dt@kernel.org>, Magnus Damm <magnus.damm@gmail.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH v2 0/3] SoC identification support for RZ/G2L Date: Wed, 9 Jun 2021 17:37:14 +0100 Message-Id: <20210609163717.3083-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk
Series	SoC identification support for RZ/G2L \| expand [v2,0/3] SoC identification support for RZ/G2L [v2,1/3] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller [v2,2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's [v2,3/3] arm64: dts: renesas: r9a07g044: Add SYSC node to RZ/G2L SoC DTSI

Message ID

20210609163717.3083-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)

Headers

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
        Rob Herring <robh+dt@kernel.org>,
        Magnus Damm <magnus.damm@gmail.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-renesas-soc@vger.kernel.org,
        Prabhakar <prabhakar.csengg@gmail.com>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 0/3] SoC identification support for RZ/G2L
Date: Wed,  9 Jun 2021 17:37:14 +0100
Message-Id: <20210609163717.3083-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Precedence: bulk

Series

SoC identification support for RZ/G2L | expand

Message

Prabhakar June 9, 2021, 4:37 p.m. UTC

Hi All,

This patch series adds support for RZ/G2{L,LC} SoC
identification.

SoC identification register is part of SYSC block and
currently no driver is added for SYSC block so just the
basic properties are added in binding documentation (and will
updated with the required properties once the driver is in
place) and this node is used in renesas-soc.c for SoC
identification.

Patches are based on top of [1] master branch and is dependent on
patch series [2].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=497355

Changes for v2:
* Added description for multiple interrupts in SYSC binding doc
* Added interrupt-names property in SYSC binding doc
* Update dtsi to included interrupt-names property for SYSC node
* Mapped entire SYSC block to read the device id
* Included RB tag for patch 1, 3

Cheers,
Prabhakar

Lad Prabhakar (3):
  dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation
    for SYSC controller
  soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC}
    SoC's
  arm64: dts: renesas: r9a07g044: Add SYSC node to RZ/G2L SoC DTSI

 .../bindings/power/renesas,rzg2l-sysc.yaml    | 63 +++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    | 12 ++++
 drivers/soc/renesas/renesas-soc.c             | 33 +++++++++-
 3 files changed, 107 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml