| Message ID | 20210803175109.1729-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Renesas RZ/G2L IRQC support | expand |
On Tue, Aug 3, 2021 at 7:51 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > Renesas RZ/G2L SoC's with below pins: > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > maximum of only 32 can be mapped to 32 GIC SPI interrupts, This looks good to me but I count on Geert to do final review, merge and send pull requests for everything Renesas. Yours, Linus Walleij
Hi All, The RZ/G2L Interrupt Controller is a front-end for the GIC found on Renesas RZ/G2L SoC's with below pins: - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a maximum of only 32 can be mapped to 32 GIC SPI interrupts, - NMI edge select. _____________ | GIC | | ________ | ____________ | | | | NMI ------------------------------------>| | SPI0-479 | | GIC-600| | _______ | |------------>| | | | | | | PPI16-31 | | | | | | IRQ0-IRQ8 | IRQC |------------>| | | P0_P48_4 ------>| GPIO |---------------->| | | |________| | | |GPIOINT0-122 | | | | | |---------------->| TINT0-31 | | | |______| |__________| |____________| The proposed RFC patches, add the IRQ domains in GPIO (pinctrl driver) and the IRQC driver. The IRQC domain handles the actual SPI interrupt and upon reception of the interrupt it propagates to the GPIO IRQ domain to handle virq. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is handled by the IRQC driver. GPIO interrupts TINT0-T31 support rising/falling/high/low trigger, support for both falling/rising edges is handled by the SW by toggling the RISING/FALLING (we might loose interrupts, I have done limited testing for SD card detection where interrupt is requested for both rising and falling edge). Please share your valuable comments on the above implementation. Cheers, Prabhakar Lad Prabhakar (4): dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller irqchip: Add RZ/G2L IA55 Interrupt Controller driver pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt arm64: dts: renesas: r9a07g044: Add IRQC node to SoC DTSI .../renesas,rzg2l-irqc.yaml | 129 ++++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 58 ++ drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-rzg2l.c | 557 ++++++++++++++++++ drivers/pinctrl/renesas/pinctrl-rzg2l.c | 205 +++++++ drivers/soc/renesas/Kconfig | 1 + 7 files changed, 959 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c