| Message ID | 20220317012404.8069-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Renesas RZ/G2L IRQC support | expand |
On Thu, Mar 17, 2022 at 5:43 AM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Hi All, > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > Renesas RZ/G2L SoC's with below pins: > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > maximum of only 32 can be mapped to 32 GIC SPI interrupts, > - NMI edge select. > > _____________ > | GIC | > | ________ | > ____________ | | | | > NMI ------------------------------------>| | SPI0-479 | | GIC-600| | > _______ | |------------>| | | > | | | | PPI16-31 | | | | > | | IRQ0-IRQ7 | IRQC |------------>| | | > P0_P48_4 ------>| GPIO |---------------->| | | |________| | > | |GPIOINT0-122 | | | | > | |---------------->| TINT0-31 | | | > |______| |__________| |____________| > > The proposed RFC patches adds hierarchical IRQ domain one in IRQC driver and other in add domain, one another > pinctrl driver. Upon interrupt requests map the interrupt to GIC. Out of GPIOINT0-122 > only 32 can be mapped to GIC SPI, this mapping is handled by the pinctrl and IRQC driver. What I want to know now is whether it is going to collide with Marc's series about GPIO IRQ chip constification?
On Thu, 17 Mar 2022 08:46:14 +0000, Andy Shevchenko <andy.shevchenko@gmail.com> wrote: > > On Thu, Mar 17, 2022 at 5:43 AM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > Hi All, > > > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > > Renesas RZ/G2L SoC's with below pins: > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > > maximum of only 32 can be mapped to 32 GIC SPI interrupts, > > - NMI edge select. > > > What I want to know now is whether it is going to collide with Marc's > series about GPIO IRQ chip constification? Probably, but the current scheme will still be alive for some time (you'll need a couple of cycles to sort out all the drivers). Worse case, this can be fixed at merge time. M.
Hi Marc, On Thu, Mar 17, 2022 at 9:23 AM Marc Zyngier <maz@kernel.org> wrote: > > On Thu, 17 Mar 2022 08:46:14 +0000, > Andy Shevchenko <andy.shevchenko@gmail.com> wrote: > > > > On Thu, Mar 17, 2022 at 5:43 AM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > > > Hi All, > > > > > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > > > Renesas RZ/G2L SoC's with below pins: > > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts > > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > > > maximum of only 32 can be mapped to 32 GIC SPI interrupts, > > > - NMI edge select. > > > > > What I want to know now is whether it is going to collide with Marc's > > series about GPIO IRQ chip constification? > > Probably, but the current scheme will still be alive for some time > (you'll need a couple of cycles to sort out all the drivers). > Ouch, thanks for letting me know. BTW there are a couple of changes to GPIO core which you have to review (this was missed in the previous version). Cheers, Prabhakar > Worse case, this can be fixed at merge time. > > M. > > -- > Without deviation from the norm, progress is not possible.
Hi All, The RZ/G2L Interrupt Controller is a front-end for the GIC found on Renesas RZ/G2L SoC's with below pins: - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a maximum of only 32 can be mapped to 32 GIC SPI interrupts, - NMI edge select. _____________ | GIC | | ________ | ____________ | | | | NMI ------------------------------------>| | SPI0-479 | | GIC-600| | _______ | |------------>| | | | | | | PPI16-31 | | | | | | IRQ0-IRQ7 | IRQC |------------>| | | P0_P48_4 ------>| GPIO |---------------->| | | |________| | | |GPIOINT0-122 | | | | | |---------------->| TINT0-31 | | | |______| |__________| |____________| The proposed RFC patches adds hierarchical IRQ domain one in IRQC driver and other in pinctrl driver. Upon interrupt requests map the interrupt to GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is handled by the pinctrl and IRQC driver. Cheers, Prabhakar Changes for v4: * Used locking while RMW * Now using interrupts property instead of interrupt-map * Patch series depends on [0] * Updated binding doc * Fixed comments pointed by Andy [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/ 20220316200633.28974-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Changes for v3: -> Re-structured the driver as a hierarchical irq domain instead of chained -> made use of IRQCHIP_* macros -> dropped locking -> Added support for IRQ0-7 interrupts -> Introduced 2 new patches for GPIOLIB -> Switched to using GPIOLIB for irqdomains in pinctrl RFC v3: https://patchwork.kernel.org/project/linux-renesas-soc/cover/ 20211110225808.16388-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ RFC v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/ 20210921193028.13099-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/ 20210803175109.1729-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Lad Prabhakar (5): dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller irqchip: Add RZ/G2L IA55 Interrupt Controller driver gpio: gpiolib: Allow free() callback to be overridden gpio: gpiolib: Add ngirq member to struct gpio_irq_chip pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt .../renesas,rzg2l-irqc.yaml | 131 +++++ drivers/gpio/gpiolib.c | 13 +- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-rzg2l.c | 462 ++++++++++++++++++ drivers/pinctrl/renesas/pinctrl-rzg2l.c | 205 ++++++++ include/linux/gpio/driver.h | 8 + 7 files changed, 823 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c