[v3,00/12] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

Message ID	20220503115557.53370-1-phil.edworthy@renesas.com (mailing list archive)
Headers	show Return-Path: <linux-renesas-soc-owner@kernel.org> From: Phil Edworthy <phil.edworthy@renesas.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Phil Edworthy <phil.edworthy@renesas.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Chris Paterson <Chris.Paterson2@renesas.com>, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 00/12] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Date: Tue, 3 May 2022 12:55:45 +0100 Message-Id: <20220503115557.53370-1-phil.edworthy@renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support \| expand [v3,00/12] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support [v3,01/12] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers [v3,02/12] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions [v3,03/12] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC [v3,04/12] dt-bindings: timer: arm,arch_timer: Add optional clock and reset [v3,05/12] clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro [v3,06/12] clk: renesas: rzg2l: Add read only versions of the clk macros [v3,07/12] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers [v3,08/12] clk: renesas: rzg2l: Make use of CLK_MON registers optional [v3,09/12] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg [v3,10/12] clk: renesas: Add RZ/V2M support using the rzg2l driver [v3,11/12] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC [v3,12/12] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK

Message ID

20220503115557.53370-1-phil.edworthy@renesas.com (mailing list archive)

Headers

From: Phil Edworthy <phil.edworthy@renesas.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Phil Edworthy <phil.edworthy@renesas.com>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Chris Paterson <Chris.Paterson2@renesas.com>,
        linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-serial@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: [PATCH v3 00/12] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK
 support
Date: Tue,  3 May 2022 12:55:45 +0100
Message-Id: <20220503115557.53370-1-phil.edworthy@renesas.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support | expand

Message

Phil Edworthy May 3, 2022, 11:55 a.m. UTC

Hello,

RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
accelerator "DRP-AI" for vision, which is Renesas' original technology.
It also has a 32-bit LPDDR4 interface and video codec (H.264).

The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
cores. The firmware is an integral part of the SoC such that the HW
User's Manual documents which of the peripheral modules are used by the
firmware.

Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
and booted via nfs. Ethernet is broadly compatible with the
etheravb-rcar-gen3 driver, but interrupts need some work so it's not
been included in this patch set.

Below blocks are enabled on Renesas RZ/V2M EVK board:
- memory
- External input clock
- CPG
- UART

Links for SoC and EVK:
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output

Sorry for cross posting the patches to multiple subsystems, as these are
just the dt-binding patches included as part of initial bringup patches.

v3:
* Feedback addressed
* Added patch [0001] for renesas,em-uart dt-bindings RZ/V2M clock for the regs
* Added patch [0004] for arm,arch_timer dt-bindings optional clock and reset
* Added patch [0005] for rzg2l clk to move the DEF_MUX array size calc into the macro
* Added patch [0006] for rzg2l clk to add read-only versions of the macros

v2:
* Removed SYS dt-bindings patch and corresponding SoC identification
as we only used the LSI version register. This can be dealt with
later on.
* Fixed em-uart dt-bindings.
* Included reviewed-by tags.

Thanks
Phil