[v4,0/2] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

Message

Phil Edworthy May 4, 2022, 9:44 a.m. UTC

Hello,

RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
accelerator "DRP-AI" for vision, which is Renesas' original technology.
It also has a 32-bit LPDDR4 interface and video codec (H.264).

The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
cores. The firmware is an integral part of the SoC such that the HW
User's Manual documents which of the peripheral modules are used by the
firmware.

Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
and booted via nfs. Ethernet is broadly compatible with the
etheravb-rcar-gen3 driver, but interrupts need some work so it's not
been included in this patch set.

Below blocks are enabled on Renesas RZ/V2M EVK board:
- memory
- External input clock
- CPG
- UART

Links for SoC and EVK:
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output


Sorry for cross posting the patches to multiple subsystems, as these are
just the dt-binding patches included as part of initial bringup patches.

v4:
 * Removed arm,arch_timer optional clock and reset
 * Removed "optional" from description of renesas,em-uart clock.

v3:
 * Feedback addressed
 * Added patch [0001] for renesas,em-uart dt-bindings RZ/V2M clock for the regs
 * Added patch [0004] for arm,arch_timer dt-bindings optional clock and reset
 * Added patch [0005] for rzg2l clk to move the DEF_MUX array size calc into the macro
 * Added patch [0006] for rzg2l clk to add read-only versions of the macros

v2:
 * Removed SYS dt-bindings patch and corresponding SoC identification
   as we only used the LSI version register. This can be dealt with
   later on.
 * Fixed em-uart dt-bindings.
 * Included reviewed-by tags.

Thanks
Phil