From patchwork Tue May 24 17:22:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 12860388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2076EC433EF for ; Tue, 24 May 2022 17:22:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239079AbiEXRWa (ORCPT ); Tue, 24 May 2022 13:22:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234441AbiEXRW3 (ORCPT ); Tue, 24 May 2022 13:22:29 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 67C536EC4A; Tue, 24 May 2022 10:22:28 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,248,1647270000"; d="scan'208";a="120749683" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 May 2022 02:22:27 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 146E9400F50C; Wed, 25 May 2022 02:22:21 +0900 (JST) From: Lad Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Sagar Kadam , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Phil Edworthy , Biju Das , Lad Prabhakar Subject: [PATCH RFC 0/2] Add PLIC support for Renesas RZ/Five SoC Date: Tue, 24 May 2022 18:22:12 +0100 Message-Id: <20220524172214.5104-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi All, This patch series adds PLIC support for Renesas RZ/Five SoC. Sending this as an RFC based on the discussion [0]. This patches have been tested with I2C and DMAC interface as these blocks have edge interrupts. [0] https://lore.kernel.org/linux-arm-kernel/87o80a7t2z.wl-maz@kernel.org/T/ Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC irqchip/sifive-plic: Add support for Renesas RZ/Five SoC .../sifive,plic-1.0.0.yaml | 38 +++++++++- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 71 ++++++++++++++++++- 3 files changed, 105 insertions(+), 5 deletions(-)