| Message ID | 20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Sagar Kadam <sagar.kadam@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC
Date: Sun, 26 Jun 2022 01:43:24 +0100
Message-Id: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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| Series |
Add PLIC support for Renesas RZ/Five SoC
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Hi All, This patch series adds PLIC support for Renesas RZ/Five SoC. Sending this as an RFC based on the discussion [0]. This patches have been tested with I2C and DMAC interface as these blocks have EDGE interrupts. [0] https://lore.kernel.org/linux-arm-kernel/87o80a7t2z.wl-maz@kernel.org/T/ v1-v2: * Fixed review comments pointed by Marc and Krzysztof. RFC-->v1: * Fixed review comments pointed by Rob and Geert. * Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC. RFC: https://lore.kernel.org/linux-renesas-soc/ 20220524172214.5104-2-prabhakar.mahadev-lad.rj@bp.renesas.com/T/ Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC irqchip/sifive-plic: Add support for Renesas RZ/Five SoC .../sifive,plic-1.0.0.yaml | 44 ++++++++++- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++- 3 files changed, 113 insertions(+), 5 deletions(-)