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[v1,0/3] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling

Message ID 20220627051257.38543-1-samuel@sholland.org (mailing list archive)
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Series irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling | expand

Message

Samuel Holland June 27, 2022, 5:12 a.m. UTC 
This is a follow-up to the series "[PATCH v2 0/2] Add PLIC support for
Renesas RZ/Five SoC"[1].

The change made there is also needed for the already-supported T-HEAD
C9xx PLIC. So this binding change is necessary before I can send the
Allwinner D1 devicetree.

[1]: https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/T/

Changes in v1:
 - Use a flag for enabling the changes instead of a variant ID
 - Use handle_edge_irq instead of handle_fasteoi_ack_irq
 - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL

Samuel Holland (3):
  dt-bindings: interrupt-controller: Require trigger type for T-HEAD
    PLIC
  irqchip/sifive-plic: Name the chip more generically
  irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling

 .../sifive,plic-1.0.0.yaml                    | 31 ++++++-
 drivers/irqchip/irq-sifive-plic.c             | 91 +++++++++++++++++--
 2 files changed, 108 insertions(+), 14 deletions(-)