From patchwork Mon Jun 27 05:12:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12896200 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80FBDC43334 for ; Mon, 27 Jun 2022 05:13:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230194AbiF0FNC (ORCPT ); Mon, 27 Jun 2022 01:13:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229714AbiF0FNB (ORCPT ); Mon, 27 Jun 2022 01:13:01 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6212ADC3; Sun, 26 Jun 2022 22:13:00 -0700 (PDT) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id C3E545C00FC; Mon, 27 Jun 2022 01:12:59 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Mon, 27 Jun 2022 01:12:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:message-id:mime-version:reply-to:sender:subject :subject:to:to; s=fm3; t=1656306779; x=1656393179; bh=dkueX+p0HF YN1z2kkJI5unMCYjLIq2dF7wkxiC1Hy0g=; b=XQ6P+XfnaI1AmNkhMSzJl0yEyP WFde2eM+YF5jN2Z2CEJ+uYF+sFJ4OLTgq3VlHjdJrExFf2QP9CZjGQuW1rkU61Av L18Ttp5KonJEj5ce3vUQ3xb4cIpfZXIE74kh/+brUn0AUS3iLTjBPBUC7pzds/k+ t6Mnm3a/jSh7Q7F0qmo7lzvlVcQnFYVI0e9Oe7PGNuLGVOsxOzNHEmOnJYfZC7zJ Yd+tTSxYqr0dR2lay4Xi4GdYab4ghofuQUwlRMNnkSEfaodBrefb9Ap9xrP1ehyG kKz63rpNi1WK0W9kV6FG7Giq78hMmaqXryxvtjmmDscZPl8sk/Kz4A8j12xw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:message-id:mime-version:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; t=1656306779; x=1656393179; bh=dkueX+p0HFYN1 z2kkJI5unMCYjLIq2dF7wkxiC1Hy0g=; b=t6SDsjptSrlFMiBuvnxyMDicrWH4T H2tTDzHLzKigA7+PGp3tkoEZTiBLb9wLGItuKAAyALZtI8VJyql5WBm9n3M7EYp0 KRv3T1Wq/n8e5cJP3FzZPKvHlf0pR7rBBBt7xSxR8whQQuLKYcBZcKuNIYgpX92U +EpSi/mgAl7u9DfSmxMm3CyIHcxsCcEdXn2OsDIyytrXKFIf3kTFzHNIVURmB7yS soHAcGiv7grHn5sl19XTmiYLfOMgEj1suynJoAjnI61NtqzfKUFqV76IzY7W2gCi 3mE/KrpChugBABaXb4SrAACcTUGD+8SVAqkdYf9bCYYA/lwImloPNV67g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrudeggedgkeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofggtgfgsehtkeertdertdejnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeefkedvudekfeehgffgteekieehhfekfeegteefgfduhfffvdehvdet keegfefgteenucffohhmrghinhepkhgvrhhnvghlrdhorhhgnecuvehluhhsthgvrhfuih iivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepshgrmhhuvghlsehshhholhhlrghn ugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 27 Jun 2022 01:12:57 -0400 (EDT) From: Samuel Holland To: Lad Prabhakar , Prabhakar , Marc Zyngier , Sagar Kadam , Paul Walmsley , Palmer Dabbelt Cc: linux-renesas-soc@vger.kernel.org, Guo Ren , Geert Uytterhoeven , Thomas Gleixner , Biju Das , Samuel Holland , Albert Ou , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v1 0/3] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling Date: Mon, 27 Jun 2022 00:12:54 -0500 Message-Id: <20220627051257.38543-1-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This is a follow-up to the series "[PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC"[1]. The change made there is also needed for the already-supported T-HEAD C9xx PLIC. So this binding change is necessary before I can send the Allwinner D1 devicetree. [1]: https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/T/ Changes in v1: - Use a flag for enabling the changes instead of a variant ID - Use handle_edge_irq instead of handle_fasteoi_ack_irq - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL Samuel Holland (3): dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC irqchip/sifive-plic: Name the chip more generically irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling .../sifive,plic-1.0.0.yaml | 31 ++++++- drivers/irqchip/irq-sifive-plic.c | 91 +++++++++++++++++-- 2 files changed, 108 insertions(+), 14 deletions(-)