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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , Rob Herring , Krzysztof Kozlowski , Oleksij Rempel , Christian Marangi , John Crispin , Kurt Kanzenbach , Mans Rullgard , Arun Ramadoss , Woojung Huh , UNGLinuxDriver@microchip.com, Claudiu Manoil , Alexandre Belloni , George McCollister , DENG Qingfang , Sean Wang , Landen Chao , Matthias Brugger , Hauke Mehrtens , Martin Blumenstingl , Aleksander Jan Bajkowski , =?utf-8?q?Alvin_=C5=A0ipraga?= , Luiz Angelo Daros de Luca , Linus Walleij , Pawel Dembicki , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Geert Uytterhoeven , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Marcin Wojtas , Marek Vasut , linux-renesas-soc@vger.kernel.org, Rasmus Villemoes , Frank Rowand Subject: [PATCH v4 net-next 00/10] Validate OF nodes for DSA shared ports Date: Thu, 18 Aug 2022 14:54:50 +0300 Message-Id: <20220818115500.2592578-1-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: AM0PR10CA0040.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:150::20) To VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b87f59f0-c342-4223-6bdd-08da8110887d X-MS-TrafficTypeDiagnostic: AM6PR04MB4085:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?KPg32eUEmBJQ7uTIRhMZtCJgNCPz?= =?utf-8?q?GYAKvp5guChblaefkp1BZATqwR6T0QHPWE6o30AMdkjdIylY4G4CLn39afC1bBjzp?= =?utf-8?q?ajT3Ivqa/O3MmfxAYG2fir/Yd2jvSxNCzNnPm14tRt70VGd5vWuq3YStKCWUp3MMa?= =?utf-8?q?W3w7Fh4uU6EahqkFUpvipWWzLHfQqS1IPF4Dusk0xnP8FS+bCe4ldl5rekg0Yx3q/?= =?utf-8?q?ot+jT0o96C2pjoFkUTQujHiOpdhFy1M72brnd4IIlL7wunlIcEznAJtN9NOs5Mo/k?= =?utf-8?q?JPRKKcYW2fdhQcL4PO92F889CB7GNc4TaJdz0bI1TYkAUr91EVGo7MQ+BmVTkN6rP?= =?utf-8?q?JMI0H4khxhlax0iBWn8/fIb1BhU32Wl+q+B3qpQgQQHqHFTGpq+6Kq5b8nmW4/lWB?= =?utf-8?q?x3wn02Nsi3O6SsP2msxDMVcoN30XHF2eMqZ16kqd/a+bAujvFDZUZptPLv14MuQvm?= =?utf-8?q?UBn5y1TzR06L7Z5J1BbEmtXbRasJtIsNcbqEYRmlNmjm4of8YxrA9tbjgV1XFdNJM?= =?utf-8?q?hCCH38LGuYWS3rPoFsi9Tws+Wb2MxwfW102CbKfkU8r9IuZm1mYd9fWhFvqymvvxC?= =?utf-8?q?PE+oxZxsy6UpHqXEANay+bAJA/Qn/jQ/75S4fdBViFt8V39eTG0EaqAd8TP3qoExI?= =?utf-8?q?CfXnyhqwIFejrG30D9RuO8KlhjhK0Fp3/P5yWdJGWazhkQOx1/xtitwLhVHOn9ZXw?= =?utf-8?q?k5wHqTKuahypup4M2mCqslc+9fy2YiYm3lftzbF0paUz4/HI6uH5CJSsvYt1BPkEs?= =?utf-8?q?3/THXSuskO1dSoHLNK7dnyP8acWzh7IFRd9uAknwaCGEYWjkvceCIMPxb5EcBCNHY?= =?utf-8?q?8/CxPfWYIniNuidscYi9Ndq9IC+HoxMnVKUm5DHcdWBaFPMw1IsuqpGYIruApJMaj?= =?utf-8?q?7voRtq1ev7MjXp3CXRnvOGmJPdOBWJHre+7NRr+Ga6f2oztu73TRQ5qu+Q3Ulvi7Z?= =?utf-8?q?cr7C3/WZgoa/RCHf5vcaJah8oQpCoNX1PojXo2w/OHTkRDexR5iQ+I86om2rQU4iq?= =?utf-8?q?4Y3U6VLCTzhSDVYejYILNwfGRGdoIaEzMg+BhQZ0qnixla+wG/Cw85gh6NYg23Td+?= =?utf-8?q?lijFDKUgodG6+KmRSkVfDXdeIos4ihgKFkil7nB7iz5Gi6iNOT/PFbU5/gFIDNxnm?= =?utf-8?q?4fe5gVlI1r0BdrvrbV5FYjMzmjwUM+lPY0ALsNjG15DeIvZGawhYfbTOpYIMRiogW?= =?utf-8?q?7iIvUKT21j54YQIu+tjJ2KcK3pGDgEb2rxbX2VesWS/+YKE485ph+7+c5hBzTqf2h?= =?utf-8?q?uGf1KsnCjBWHQrNlfkBqi8yT2IiTMQZJSSE6Kas8nXyGy2+yV21aIrfKYbQyPVHkG?= =?utf-8?q?UPwdKgMXbu+UYJrKeHnvoJ28piZf9mz4+jxKEnqdffAUZ96qCbvODUzoqX5c3jBrG?= =?utf-8?q?qGieIiPC9gpHXbkOXAp7+UyDRGK3TgoDvzMIxWQiC+9xVLVAN5pFimi22MNJFbsAe?= =?utf-8?q?GtiJ2TNPwBOGa3ULAZfQ3EwkbT9MXZRWPvL9oD/3NHGIilxDe7AqQKiZrnZg6Qr/n?= =?utf-8?q?ffWyTdD0xEcJ/sagjVwwWrj96LOzZaulgg=3D=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b87f59f0-c342-4223-6bdd-08da8110887d X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2022 11:55:23.7602 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zWEkZfhtSxAg8MrBcTMrRDeJvZY552DVLQpeYLN7x9ct65zArZUwnQ2U6ZctDN5hlRIh4abjnIeLOF1pL5bfHg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4085 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This is the first set of measures taken so that more drivers can be transitioned towards phylink on shared (CPU and DSA) ports some time in the future. It consists of: - expanding the DT schema for DSA and related drivers to clarify the new requirements. - introducing warnings for drivers that currently skip phylink due to incomplete DT descriptions. - introducing warning for drivers that currently skip phylink due to using platform data (search for struct dsa_chip_data). - closing the possibility for new(ish) drivers to skip phylink, by validating their DT descriptions. - making the code paths used by shared ports more evident. - preparing the code paths used by shared ports for further work to fake a link description where that is possible. More details in patch 10/10. DT binding (patches 1-6) and kernel (7-10) are in principle separable, but are submitted together since they're part of the same story. Patches 8 and 9 are DSA cleanups, and patch 7 is a dependency for patch 10. Submitting as RFC because it's RFC season, but I'd like to resend this for proper inclusion as soon as possible once the merge window closes, so ACKs/NACKs are welcome. Change log in patches. v1 at https://patchwork.kernel.org/project/netdevbpf/patch/20220723164635.1621911-1-vladimir.oltean@nxp.com/ v2 at https://patchwork.kernel.org/project/netdevbpf/patch/20220729132119.1191227-5-vladimir.oltean@nxp.com/ v3 at https://patchwork.kernel.org/project/netdevbpf/cover/20220806141059.2498226-1-vladimir.oltean@nxp.com/ Cc: Rob Herring Cc: Frank Rowand Vladimir Oltean (10): dt-bindings: net: dsa: xrs700x: add missing CPU port phy-mode to example dt-bindings: net: dsa: hellcreek: add missing CPU port phy-mode/fixed-link to example dt-bindings: net: dsa: b53: add missing CPU port phy-mode to example dt-bindings: net: dsa: microchip: add missing CPU port phy-mode to example dt-bindings: net: dsa: rzn1-a5psw: add missing CPU port phy-mode to example dt-bindings: net: dsa: make phylink bindings required for CPU/DSA ports of: base: export of_device_compatible_match() for use in modules net: dsa: avoid dsa_port_link_{,un}register_of() calls with platform data net: dsa: rename dsa_port_link_{,un}register_of net: dsa: make phylink-related OF properties mandatory on DSA and CPU ports .../bindings/net/dsa/arrow,xrs700x.yaml | 2 + .../devicetree/bindings/net/dsa/brcm,b53.yaml | 2 + .../devicetree/bindings/net/dsa/dsa-port.yaml | 17 ++ .../net/dsa/hirschmann,hellcreek.yaml | 6 + .../bindings/net/dsa/microchip,ksz.yaml | 4 + .../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 2 + drivers/of/base.c | 1 + net/dsa/dsa2.c | 36 +++- net/dsa/dsa_priv.h | 4 +- net/dsa/port.c | 190 ++++++++++++++++-- 10 files changed, 237 insertions(+), 27 deletions(-)