| Message ID | 20240222083946.3977135-1-peterlin@andestech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Support Andes PMU extension | expand |
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Thu, 22 Feb 2024 16:39:36 +0800 you wrote: > Hi All, > > This patch series introduces the Andes PMU extension, which serves the > same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt > is assigned to bit 18 in the custom S-mode local interrupt enable and > pending registers (slie/slip), while the interrupt cause is (256 + 18). > > [...] Here is the summary with links: - [v9,01/10] riscv: errata: Rename defines for Andes https://git.kernel.org/riscv/c/be5e8872b3fb - [v9,02/10] irqchip/riscv-intc: Allow large non-standard interrupt number https://git.kernel.org/riscv/c/96303bcb401c - [v9,03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller https://git.kernel.org/riscv/c/f4cc33e78ba8 - [v9,04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string https://git.kernel.org/riscv/c/b88727d554f0 - [v9,05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC https://git.kernel.org/riscv/c/95113bb70515 - [v9,06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations https://git.kernel.org/riscv/c/ea0e0178e101 - [v9,07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling https://git.kernel.org/riscv/c/bc969d6cc96a - [v9,08/10] dt-bindings: riscv: Add Andes PMU extension description https://git.kernel.org/riscv/c/61609bf2b29d - [v9,09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f https://git.kernel.org/riscv/c/270fc77e7b0e - [v9,10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events https://git.kernel.org/riscv/c/f5102e31c209 You are awesome, thank you!
Hi All, This patch series introduces the Andes PMU extension, which serves the same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt is assigned to bit 18 in the custom S-mode local interrupt enable and pending registers (slie/slip), while the interrupt cause is (256 + 18). The series can be found on Andes Technology GitHub: - https://github.com/andestech/linux/commits/andes-pmu-support-v9 The PMU device tree node used on AX45MP: - https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3 Locus Wei-Han Chen (1): riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin (9): riscv: errata: Rename defines for Andes irqchip/riscv-intc: Allow large non-standard interrupt number irqchip/riscv-intc: Introduce Andes hart-level interrupt controller dt-bindings: riscv: Add Andes interrupt controller compatible string riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC perf: RISC-V: Eliminate redundant interrupt enable/disable operations perf: RISC-V: Introduce Andes PMU to support perf event sampling dt-bindings: riscv: Add Andes PMU extension description riscv: dts: renesas: Add Andes PMU extension for r9a07g043f .../devicetree/bindings/riscv/cpus.yaml | 6 +- .../devicetree/bindings/riscv/extensions.yaml | 7 + arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/errata/andes/errata.c | 10 +- arch/riscv/include/asm/errata_list.h | 13 +- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/alternative.c | 2 +- arch/riscv/kernel/cpufeature.c | 1 + drivers/irqchip/irq-riscv-intc.c | 82 +++++++++-- drivers/perf/Kconfig | 14 ++ drivers/perf/riscv_pmu_sbi.c | 37 ++++- include/linux/soc/andes/irq.h | 18 +++ .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++ .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + 18 files changed, 488 insertions(+), 39 deletions(-) create mode 100644 include/linux/soc/andes/irq.h create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json