mbox series

[v2,0/4] Add SoC identification for Renesas RZ/V2H SoC

Message ID 20240227232531.218159-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
Headers show
Series Add SoC identification for Renesas RZ/V2H SoC | expand

Message

Lad, Prabhakar Feb. 27, 2024, 11:25 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi all,

This patch series aims to add SoC identification support for the Renesas
RZ/V2H SoC.

v1 - > v2
- Replaced RZ/V2H{P} -> RZ/V2H(P)
- Included Ack from Krzysztof for patch #1
- Included RB from Geert for patch #1 and #4
- Dropped extal_clk node from patch #2
- Used small case for hex value in patch #3

v1:
- https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240219160912.1206647-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

RZ/V2H boot logs:
------------------
~ # uname -raLinux rz/v2h 6.8.0-rc6-arm64-renesas+ #229 SMP PREEMPT Tue Feb 27 21:11:51 GMT 2024 aarch64 GNU/Linux
~ #
~ # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
soc0/$i; done
machine: Renesas EVK based on r9a09g057h44
family: RZ/V2H
soc_id: r9a09g057
revision: 0
~ #
~ # cat /proc/cpuinfo
processor       : 0
BogoMIPS        : 48.00
Features        : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 1
BogoMIPS        : 48.00
Features        : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 2
BogoMIPS        : 48.00
Features        : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 3
BogoMIPS        : 48.00
Features        : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

~ #
~ #
------------------

Cheers,
Prabhakar

Lad Prabhakar (4):
  dt-bindings: soc: renesas: Document Renesas RZ/V2H(P) SoC variants
  dt-bindings: arm: renesas: Document Renesas RZ/V2H(P) System
    Controller
  soc: renesas: Add identification support for RZ/V2H SoC
  arm64: defconfig: Enable R9A09G057 SoC

 .../soc/renesas/renesas,r9a09g057-sys.yaml    | 51 +++++++++++++++++++
 .../bindings/soc/renesas/renesas.yaml         |  8 +++
 arch/arm64/configs/defconfig                  |  1 +
 drivers/soc/renesas/Kconfig                   |  5 ++
 drivers/soc/renesas/renesas-soc.c             | 20 +++++++-
 5 files changed, 84 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml