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([2401:4900:1c07:3bcb:e05d:a577:9add:a9ce]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f63240c947sm450105ad.269.2024.05.30.10.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 10:41:40 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Claudiu Beznea , Fabrizio Castro , Paul Barker , Lad Prabhakar Subject: [PATCH v3 00/15] Add PFC support for Renesas RZ/V2H(P) SoC Date: Thu, 30 May 2024 18:38:42 +0100 Message-Id: <20240530173857.164073-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Hi All, This patch series aims to add PFC (Pin Function Controller) support for Renesas RZ/V2H(P) SoC. The PFC block on RZ/V2H(P) is almost similar to one found on the RZ/G2L family with couple of differences. To able to re-use the use the existing driver for RZ/V2H(P) SoC function pointers are introduced based on the SoC changes. v2->v3 - Dropped patch 1/13 [0] as its been already queued up. - Updated description for renesas,output-impedance property - Added three new patches 02/15, 04/15 and 14/15 - Updated size for cfg in struct rzg2l_variable_pin_cfg - Included RB tags - Introduced single function pointer to (un)lock PFC - Now passing offset to pmc_writeb() instead of virtual address - Renamed read_oen->oen_read - Renamed write_oen->oen_write - Renamed get_bias_param -> hw_to_bias_param - Renamed get_bias_val -> bias_param_to_hw - Dropped un-necessary block {} - Now reading arg before calling hw_to_bias_param() - Added gaurd for custom_conf_items in struct rzg2l_pinctrl_data - Renamed PIN_CFG_OPEN_DRAIN->PIN_CFG_NOD - Renamed PIN_CFG_SCHMIT_CTRL->PIN_CFG_SMT - Introduced PWPR_REGWE_A instead of using PWPR_PFCWE - Dropped using pwpr_lock - Optimized rzv2h_pin_to_oen_bit() RFC->v2 - Fixed review comments pointed by Rob - Incorporated changes suggested by Claudiu - Fixed build error reported for m68K - Dropped IOLH groups as we will be passing register values - Fixed configs for dedicated pins - Added support for slew-rate and bias settings - Added support for OEN RFC: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240423175900.702640-2-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (15): dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC pinctrl: renesas: pinctrl-rzg2l: Rename B0WI to BOWI pinctrl: renesas: pinctrl-rzg2l: Allow more bits for pin configuration pinctrl: renesas: pinctrl-rzg2l: Drop struct rzg2l_variable_pin_cfg pinctrl: renesas: pinctrl-rzg2l: Allow parsing of variable configuration for all architectures pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH pinctrl: renesas: pinctrl-rzg2l: Add function pointer for locking/unlocking the PFC register pinctrl: renesas: pinctrl-rzg2l: Add function pointer for writing to PMC register pinctrl: renesas: pinctrl-rzg2l: Add function pointers for reading/writing OEN register pinctrl: renesas: pinctrl-rzg2l: Add support to configure the slew-rate pinctrl: renesas: pinctrl-rzg2l: Add support to set pulling up/down the pins pinctrl: renesas: pinctrl-rzg2l: Pass pincontrol device pointer to pinconf_generic_parse_dt_config() pinctrl: renesas: pinctrl-rzg2l: Add support for custom parameters pinctrl: renesas: pinctrl-rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc() pinctrl: renesas: pinctrl-rzg2l: Add support for RZ/V2H SoC .../pinctrl/renesas,rzg2l-pinctrl.yaml | 23 +- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 773 ++++++++++++++---- 2 files changed, 619 insertions(+), 177 deletions(-)