| Message ID | 20240730122436.350013-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: dts: renesas: Correct GICD and GICR sizes | expand |
Hi Prabhakar, On Tue, Jul 30, 2024 at 2:26 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > This patch series aims to correct GICD and GICR sizes on RZ/G2L(LC), > RZ/G2UL, RZ/V2L and RZ/G3S SoCs. These SoCs are equipped with GIC-600. > > GIC-600 supports MBI by default, so GICD size is set to 128kB. > On RZ/G2UL and RZ/G3S SoC despite being single core the GICR size is set > to 256kB as dumping the GICR_IIDR register shows it has two instances of > GICR. > > v1->v2 > - Dropped changes for single core > - Updated commit message Thanks for your series! I have to trust you on this, and will queue this series in renesas-devel for v6.12, with s/kB/KiB/g. Gr{oetje,eeting}s, Geert
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi All, This patch series aims to correct GICD and GICR sizes on RZ/G2L(LC), RZ/G2UL, RZ/V2L and RZ/G3S SoCs. These SoCs are equipped with GIC-600. GIC-600 supports MBI by default, so GICD size is set to 128kB. On RZ/G2UL and RZ/G3S SoC despite being single core the GICR size is set to 256kB as dumping the GICR_IIDR register shows it has two instances of GICR. v1->v2 - Dropped changes for single core - Updated commit message Cheers, Prabhakar Lad Prabhakar (4): arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes arm64: dts: renesas: r9a07g043u: Correct GICD and GICR sizes arm64: dts: renesas: r9a07g054: Correct GICD and GICR sizes arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-)