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AJvYcCXX3AM4TaPehR4Ty/GyIrw2QvIDAgZwB0GjU4HJ/FHOGEQ/DAMdBbu0l+Oxs2T5TeswxTo0YLMvrcbcbdkGrdVHT2FAIuKNgVtMEsNaTm8b07xrQIoqC9vtKP/c9Z9Tfg2CpP+tNbVK X-Gm-Message-State: AOJu0Yyz3IDO5W+kULobt59oo5ENsPX+33a+oUJObNnxAonBu4rdOyow q4tuR0Bi92H8jbp99tQ/z/kIZoQZsusSiHvk4XgG/vwwEXk3jQDi X-Google-Smtp-Source: AGHT+IELmjxvOLpZpyjp46/lip7mAwMXg9akl0FqzFsJbWjnkaKfABQ4ySxCm4fWC9qv/tPvchwLfw== X-Received: by 2002:a05:600c:1987:b0:426:641f:25e2 with SMTP id 5b1f17b1804b1-428e6b7e80bmr78356715e9.25.1722886770257; Mon, 05 Aug 2024 12:39:30 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:25b8:5324:d26c:319c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-428e6e4f5b6sm151496395e9.25.2024.08.05.12.39.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 12:39:29 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 0/2] clk: renesas: rzv2h-cpg: Add divider clock support Date: Mon, 5 Aug 2024 20:38:44 +0100 Message-Id: <20240805193846.52416-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Hi All, This patch series aims to add divider clock support and add clock and reset entries for below IP blocks for RZ/V2H(P) SoC, - GTM - WDT - RIIC - SDHI Cheers, Prabhakar Lad Prabhakar (2): clk: renesas: rzv2h-cpg: Add support for dynamic switching divider clocks clk: renesas: r9a09g057-cpg: Add clock and reset entries for GTM/RIIC/SDHI/WDT drivers/clk/renesas/r9a09g057-cpg.c | 84 ++++++++++++++ drivers/clk/renesas/rzv2h-cpg.c | 163 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 14 +++ 3 files changed, 261 insertions(+)