[v3,0/3] Add clock driver support for Renesas RZ/G3E SoC

Message

Biju Das Dec. 13, 2024, 12:35 p.m. UTC

Hi all,

This patch series adds clock driver support for RZ/G3E. Also add
MSTOP support for RZ/V2H.

This patch series is tested on renesas-devel and next.

v2->v3:
 * Updated commit header and description for this series as all the
   patches accepted except clock.
 * Updated commit description for patch#1 as adding MSTOP support
   for RZ/V2H first will ease backporting.
 * Added missing MSTOP data for SD{0,1,2}
 * Replaced BUS_MSTOP_NO_DATA->BUS_MSTOP_NONE
 * Added idx, mask variable to struct rzv2h_mstop to simplify
   the code.
 * Started setting initial value of refcount with the correct value
   based on the clock's current state.
 * Collected tags.
v1->v2:
 * Collected tags.
 * Fixed typo "CORE_CLK*"->"CORECLK*" to match with hardware manual in the
   clk bindings.
 * Added MSTOP data for RZ/V2H CRU IP.
 * Fixed typo clock->clk in error path of rzv2h_cpg_register_mod_clk().
 * Added OPP table support for frequency scaling.

Biju Das (3):
  clk: renesas: rzv2h-cpg: Add MSTOP support
  clk: renesas: rzv2h-cpg: Add support for RZ/G3E SoC
  clk: renesas: r9a09g047: Add CA55 core clocks

 drivers/clk/renesas/Kconfig         |   7 +-
 drivers/clk/renesas/Makefile        |   1 +
 drivers/clk/renesas/r9a09g047-cpg.c | 116 +++++++++++++++++++++
 drivers/clk/renesas/r9a09g057-cpg.c | 153 ++++++++++++++++++----------
 drivers/clk/renesas/rzv2h-cpg.c     | 105 ++++++++++++++++++-
 drivers/clk/renesas/rzv2h-cpg.h     |  24 +++--
 6 files changed, 344 insertions(+), 62 deletions(-)
 create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c