[v5,0/5] soc: renesas: Add RZ/G3E SoC detection support

Message

John Madieu Jan. 28, 2025, 3:13 a.m. UTC

This patch series adds SoC detection support for the RZ/G3E, RZ/V2H(P),
and the RZ/G2Si SoCs. While the previous series (v1 and v2) were adding
syscon support as well, this series drops it to get rid of not-merged
dependencies. Syscon support will be added when adding one of its user
(such as TSU, PCIe, or USB drivers).
                                                                                                                                               
This Soc detection series relies on the System Controller IP to detect
various SoC features like core count, NPU/GPU/ISP presence, and CA55 PLL
configuration.

Key features:                                          
- Detection of SoC revision                          
- Detection of quad/dual core configuration                          
- Detection of Ethos-U55 NPU presence                         
- Validation of CA55 PLL frequency setting
- SoC-specific extended identification through callbacks

Changes in v5:
- Use proper hex values for SoC-specific register offset and mask and avoid using common
  included file
- Added some sanity check while grabbing SoC ID compatible string
- Fixed some minor typos
- Styled code as recommanded by Geert

Changes in v4:
- Fixed typo in commit message
- Restored Rob's Rb tag

Changes in v3:                                        
- Got rid of [1] and other not-merged dependencies
- Removed syscon/regmap support
- Added RZ/V2H SoC detection support

Changes in v2:
- Fixed code style issues in rz-sysc.c and r9a09g047-sysc.c
- Fixed device tree documentation, getting rid of syscon compatible string
- Handled non signal-aware readable/writeable regmap callback
- Consolidated common code between RZ/V2H and RZ/G3E drivers
- Moved SoC ID detection from the compatible string fix into a new patch

Tested:
- Example of SoC detection:
[    0.065608] renesas-rz-sysc 10430000.system-controller: Detected Renesas
Quad Core RZ/G3E r9a09g047 Rev 0  with Ethos-U55

- Example of PLL misconfiguration warning:
[    0.065616] renesas-rz-sysc 10430000.system-controller: CA55 PLL is not
set to 1.7GHz

[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=912455


Claudiu Beznea (2):
  soc: renesas: Add SYSC driver for Renesas RZ family
  soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driver

John Madieu (3):
  soc: renesas: rz-sysc: Add support for RZ/G3E family
  soc: renesas: rz-sysc: Move RZ/V2H SoC detection to the SYS driver
  soc: renesas: rzv2h: Add a callback to print SoC-specific extra
    features

 drivers/soc/renesas/Kconfig          |  18 ++++
 drivers/soc/renesas/Makefile         |   4 +
 drivers/soc/renesas/r9a08g045-sysc.c |  23 +++++
 drivers/soc/renesas/r9a09g047-sys.c  |  66 +++++++++++++
 drivers/soc/renesas/r9a09g057-sys.c  |  66 +++++++++++++
 drivers/soc/renesas/renesas-soc.c    |  33 +------
 drivers/soc/renesas/rz-sysc.c        | 136 +++++++++++++++++++++++++++
 drivers/soc/renesas/rz-sysc.h        |  46 +++++++++
 8 files changed, 360 insertions(+), 32 deletions(-)
 create mode 100644 drivers/soc/renesas/r9a08g045-sysc.c
 create mode 100644 drivers/soc/renesas/r9a09g047-sys.c
 create mode 100644 drivers/soc/renesas/r9a09g057-sys.c
 create mode 100644 drivers/soc/renesas/rz-sysc.c
 create mode 100644 drivers/soc/renesas/rz-sysc.h