| Message ID | 20250401171432.101504-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add USB2PHY Port Reset Control driver for Renesas RZ/V2H(P) SoC | expand |
On Tue, Apr 01, 2025 at 06:14:29PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Hi All, > > This patch series adds support for the USB2PHY Port Reset control driver > for the Renesas RZ/V2H(P) SoC. The changes include documenting the USB2PHY > Port Reset control bindings and adding the driver. > > v2->v3 > - Dropped Acks from Conor and Fabrizio, due to below changes > - Renamed binding renesas,rzv2h-usb2phy-ctrl.yaml to > renesas,rzv2h-usb2phy-reset.yaml That's not really justifying dropping review. Still not possible to compare it: b4 diff '20250401171432.101504-1-prabhakar.mahadev-lad.rj@bp.renesas.com' Grabbing thread from lore.kernel.org/all/20250401171432.101504-1-prabhakar.mahadev-lad.rj@bp.renesas.com/t.mbox.gz Checking for older revisions Grabbing search results from lore.kernel.org Nothing matching that query. --- Analyzing 4 messages in the thread Could not find lower series to compare against. Best regards, Krzysztof
Hi Krzysztof, On Wed, Apr 2, 2025 at 7:57 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Tue, Apr 01, 2025 at 06:14:29PM +0100, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Hi All, > > > > This patch series adds support for the USB2PHY Port Reset control driver > > for the Renesas RZ/V2H(P) SoC. The changes include documenting the USB2PHY > > Port Reset control bindings and adding the driver. > > > > v2->v3 > > - Dropped Acks from Conor and Fabrizio, due to below changes > > - Renamed binding renesas,rzv2h-usb2phy-ctrl.yaml to > > renesas,rzv2h-usb2phy-reset.yaml > > That's not really justifying dropping review. > I was in two minds here. > Still not possible to compare it: > > b4 diff '20250401171432.101504-1-prabhakar.mahadev-lad.rj@bp.renesas.com' > Grabbing thread from lore.kernel.org/all/20250401171432.101504-1-prabhakar.mahadev-lad.rj@bp.renesas.com/t.mbox.gz > Checking for older revisions > Grabbing search results from lore.kernel.org > Nothing matching that query. I did get the same, does `b4` look for matching subjects, I ask because I changed between v2 and v3. Below are the changes from v2 -> v3: $ b4 diff -m PATCH-v2-0-2-Add-USB2PHY-control-support-for-Renesas-RZ-V2H-P-SoC.mbox PATCH-v3-0-3-Add-USB2PHY-Port-Reset-Control-driver-for-Renesas-RZ-V2H-P-SoC.mbox Loading 20 messages from PATCH-v2-0-2-Add-USB2PHY-control-support-for-Renesas-RZ-V2H-P-SoC.mbox Loading 7 messages from PATCH-v3-0-3-Add-USB2PHY-Port-Reset-Control-driver-for-Renesas-RZ-V2H-P-SoC.mbox --- Diffing v2 and v3 Running: git range-diff b88e506a8af0..a85d31383c56 84cdef6f74a8..e90a30abcf89 --- 1: 093fce8efcbc ! 1: 73c076c4ea0b dt-bindings: reset: Document RZ/V2H(P) USB2PHY Control @@ Metadata Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> ## Commit message ## - dt-bindings: reset: Document RZ/V2H(P) USB2PHY Control + dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset driver - Add device tree binding document for the Renesas RZ/V2H(P) USB2PHY Control - Device. It mainly controls reset and power down of the USB2.0 PHY (for - both host and function). + Add a device tree binding document for the Renesas RZ/V2H(P) USB2PHY reset + driver. This driver controls the reset and power-down of the USB2.0 PHY, + which is used for both host and function modes. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> - ## Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-ctrl.yaml (new) ## + ## Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml (new) ## @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- -+$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-ctrl.yaml# ++$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + -+title: Renesas RZ/V2H(P) USB2PHY Control ++title: Renesas RZ/V2H(P) USB2PHY Port reset Control + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: -+ The RZ/V2H(P) USB2PHY Control mainly controls reset and power down of the ++ The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the + USB2.0 PHY. + +properties: + compatible: -+ const: renesas,r9a09g057-usb2phy-ctrl # RZ/V2H(P) ++ const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P) + + reg: + maxItems: 1 @@ Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-ctrl.yaml (new) + - | + #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> + -+ usbphy-ctrl@15830000 { -+ compatible = "renesas,r9a09g057-usb2phy-ctrl"; ++ reset-controller@15830000 { ++ compatible = "renesas,r9a09g057-usb2phy-reset"; + reg = <0x15830000 0x10000>; + clocks = <&cpg CPG_MOD 0xb6>; + resets = <&cpg 0xaf>; 2: a85d31383c56 ! 2: 8c715db41c21 reset: Add USB2PHY control driver for Renesas RZ/V2H(P) @@ Metadata Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> ## Commit message ## - reset: Add USB2PHY control driver for Renesas RZ/V2H(P) + reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P) - Add support for the USB2PHY control driver on the Renesas RZ/V2H(P) SoC. - Make the driver handle reset and power-down operations for the USB2PHY. + Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC. + Enable control of USB2.0 PHY reset and power-down operations, including + assert and deassert functionalities for the PHY. - Pass OF data to support future SoCs with similar USB2PHY hardware but - different register configurations. Define device-specific initialization - values and control register settings in OF data to ensure flexibility - for upcoming SoCs. + Leverage device tree (OF) data to support future SoCs with similar USB2PHY + hardware but varying register configurations. Define initialization values + and control register settings to ensure flexibility for upcoming platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> @@ drivers/reset/Kconfig: config RESET_RZG2L_USBPHY_CTRL Support for USBPHY Control found on RZ/G2L family. It mainly controls reset and power down of the USB/PHY. -+config RESET_RZV2H_USB2PHY_CTRL -+ tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY control driver" ++config RESET_RZV2H_USB2PHY ++ tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" + depends on ARCH_RENESAS || COMPILE_TEST + help -+ Support for USB2PHY Control found on the RZ/V2H(P) SoC (and similar SoCs). -+ It mainly controls reset and power down of the USB2 PHY. ++ Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC ++ (and similar SoCs). + config RESET_SCMI tristate "Reset driver controlled via ARM SCMI interface" @@ drivers/reset/Makefile: obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o -+obj-$(CONFIG_RESET_RZV2H_USB2PHY_CTRL) += reset-rzv2h-usb2phy-ctrl.o ++obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o - ## drivers/reset/reset-rzv2h-usb2phy-ctrl.c (new) ## + ## drivers/reset/reset-rzv2h-usb2phy.c (new) ## @@ +// SPDX-License-Identifier: GPL-2.0 +/* -+ * Renesas RZ/V2H(P) USB2PHY control driver ++ * Renesas RZ/V2H(P) USB2PHY Port reset control driver + * + * Copyright (C) 2025 Renesas Electronics Corporation + */ @@ drivers/reset/reset-rzv2h-usb2phy-ctrl.c (new) + u16 val; +}; + -+struct rzv2h_usb2phy_data { ++struct rzv2h_usb2phy_reset_of_data { + const struct rzv2h_usb2phy_regval *init_vals; + unsigned int init_val_count; + -+ u16 ctrl_reg; -+ u16 ctrl_assert_val; -+ u16 ctrl_deassert_val; -+ u16 ctrl_status_bits; -+ u16 ctrl_release_val; ++ u16 reset_reg; ++ u16 reset_assert_val; ++ u16 reset_deassert_val; ++ u16 reset_status_bits; ++ u16 reset_release_val; + -+ u16 ctrl2_reg; -+ u16 ctrl2_acquire_val; -+ u16 ctrl2_release_val; ++ u16 reset2_reg; ++ u16 reset2_acquire_val; ++ u16 reset2_release_val; +}; + -+struct rzv2h_usb2phy_ctrl_priv { -+ const struct rzv2h_usb2phy_data *data; ++struct rzv2h_usb2phy_reset_priv { ++ const struct rzv2h_usb2phy_reset_of_data *data; + void __iomem *base; + struct device *dev; + struct reset_controller_dev rcdev; -+ spinlock_t lock; ++ spinlock_t lock; /* protects register accesses */ +}; + -+#define rcdev_to_priv(x) container_of(x, struct rzv2h_usb2phy_ctrl_priv, rcdev) ++static inline struct rzv2h_usb2phy_reset_priv ++*rzv2h_usbphy_rcdev_to_priv(struct reset_controller_dev *rcdev) ++{ ++ return container_of(rcdev, struct rzv2h_usb2phy_reset_priv, rcdev); ++} + -+static int rzv2h_usbphy_ctrl_assert(struct reset_controller_dev *rcdev, -+ unsigned long id) ++/* This function must be called only after pm_runtime_resume_and_get() has been called */ ++static void rzv2h_usbphy_assert_helper(struct rzv2h_usb2phy_reset_priv *priv) +{ -+ struct rzv2h_usb2phy_ctrl_priv *priv = rcdev_to_priv(rcdev); -+ const struct rzv2h_usb2phy_data *data = priv->data; ++ const struct rzv2h_usb2phy_reset_of_data *data = priv->data; ++ ++ scoped_guard(spinlock, &priv->lock) { ++ writel(data->reset2_acquire_val, priv->base + data->reset2_reg); ++ writel(data->reset_assert_val, priv->base + data->reset_reg); ++ } ++ ++ usleep_range(11, 20); ++} ++ ++static int rzv2h_usbphy_reset_assert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); + struct device *dev = priv->dev; + int ret; + @@ drivers/reset/reset-rzv2h-usb2phy-ctrl.c (new) + dev_err(dev, "pm_runtime_resume_and_get failed\n"); + return ret; + } -+ scoped_guard(spinlock, &priv->lock) { -+ writel(data->ctrl2_acquire_val, priv->base + data->ctrl2_reg); -+ writel(data->ctrl_assert_val, priv->base + data->ctrl_reg); -+ } + -+ /* The reset line needs to be asserted for more than 10 microseconds. */ -+ udelay(11); ++ rzv2h_usbphy_assert_helper(priv); ++ + pm_runtime_put(dev); + + return 0; +} + -+static int rzv2h_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev, -+ unsigned long id) ++static int rzv2h_usbphy_reset_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) +{ -+ struct rzv2h_usb2phy_ctrl_priv *priv = rcdev_to_priv(rcdev); -+ const struct rzv2h_usb2phy_data *data = priv->data; ++ struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); ++ const struct rzv2h_usb2phy_reset_of_data *data = priv->data; + struct device *dev = priv->dev; + int ret; + @@ drivers/reset/reset-rzv2h-usb2phy-ctrl.c (new) + } + + scoped_guard(spinlock, &priv->lock) { -+ writel(data->ctrl_deassert_val, priv->base + data->ctrl_reg); -+ writel(data->ctrl2_release_val, priv->base + data->ctrl2_reg); -+ writel(data->ctrl_release_val, priv->base + data->ctrl_reg); ++ writel(data->reset_deassert_val, priv->base + data->reset_reg); ++ writel(data->reset2_release_val, priv->base + data->reset2_reg); ++ writel(data->reset_release_val, priv->base + data->reset_reg); + } + + pm_runtime_put(dev); @@ drivers/reset/reset-rzv2h-usb2phy-ctrl.c (new) + return 0; +} + -+static int rzv2h_usbphy_ctrl_status(struct reset_controller_dev *rcdev, -+ unsigned long id) ++static int rzv2h_usbphy_reset_status(struct reset_controller_dev *rcdev, ++ unsigned long id) +{ -+ struct rzv2h_usb2phy_ctrl_priv *priv = rcdev_to_priv(rcdev); ++ struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); + struct device *dev = priv->dev; + int ret; + u32 reg; @@ drivers/reset/reset-rzv2h-usb2phy-ctrl.c (new) + return ret; + } + -+ scoped_guard(spinlock, &priv->lock) -+ reg = readl(priv->base + priv->data->ctrl_reg); ++ reg = readl(priv->base + priv->data->reset_reg); + + pm_runtime_put(dev); + -+ return (reg & priv->data->ctrl_status_bits) == priv->data->ctrl_status_bits; ++ return (reg & priv->data->reset_status_bits) == priv->data->reset_status_bits; +} + -+static const struct reset_control_ops rzv2h_usbphy_ctrl_reset_ops = { -+ .assert = rzv2h_usbphy_ctrl_assert, -+ .deassert = rzv2h_usbphy_ctrl_deassert, -+ .status = rzv2h_usbphy_ctrl_status, ++static const struct reset_control_ops rzv2h_usbphy_reset_ops = { ++ .assert = rzv2h_usbphy_reset_assert, ++ .deassert = rzv2h_usbphy_reset_deassert, ++ .status = rzv2h_usbphy_reset_status, +}; + -+static int rzv2h_reset_of_xlate(struct reset_controller_dev *rcdev, -+ const struct of_phandle_args *reset_spec) ++static int rzv2h_usb2phy_reset_of_xlate(struct reset_controller_dev *rcdev, ++ const struct of_phandle_args *reset_spec) +{ + /* No special handling needed, we have only one reset line per device */ + return 0; +} + -+static int rzv2h_usb2phy_ctrl_probe(struct platform_device *pdev) ++static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev) +{ -+ const struct rzv2h_usb2phy_data *data; -+ struct rzv2h_usb2phy_ctrl_priv *priv; ++ const struct rzv2h_usb2phy_reset_of_data *data; ++ struct rzv2h_usb2phy_reset_priv *priv; + struct device *dev = &pdev->dev; + struct reset_control *rstc; + int error; @@ drivers/reset/reset-rzv2h-usb2phy-ctrl.c (new) + for (unsigned int i = 0; i < data->init_val_count; i++) + writel(data->init_vals[i].val, priv->base + data->init_vals[i].reg); + ++ /* keep usb2phy in asserted state */ ++ rzv2h_usbphy_assert_helper(priv); ++ + pm_runtime_put(dev); + -+ priv->rcdev.ops = &rzv2h_usbphy_ctrl_reset_ops; ++ priv->rcdev.ops = &rzv2h_usbphy_reset_ops; + priv->rcdev.of_reset_n_cells = 0; + priv->rcdev.nr_resets = 1; -+ priv->rcdev.of_xlate = rzv2h_reset_of_xlate; ++ priv->rcdev.of_xlate = rzv2h_usb2phy_reset_of_xlate; + priv->rcdev.of_node = dev->of_node; + priv->rcdev.dev = dev; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + ++/* ++ * initialization values required to prepare the PHY to receive ++ * assert and deassert requests. ++ */ +static const struct rzv2h_usb2phy_regval rzv2h_init_vals[] = { + { .reg = 0xc10, .val = 0x67c }, + { .reg = 0xc14, .val = 0x1f }, + { .reg = 0x600, .val = 0x909 }, +}; + -+static const struct rzv2h_usb2phy_data rzv2h_of_data = { ++static const struct rzv2h_usb2phy_reset_of_data rzv2h_reset_of_data = { + .init_vals = rzv2h_init_vals, + .init_val_count = ARRAY_SIZE(rzv2h_init_vals), -+ .ctrl_reg = 0, -+ .ctrl_assert_val = 0x206, -+ .ctrl_status_bits = BIT(2), -+ .ctrl_deassert_val = 0x200, -+ .ctrl_release_val = 0x0, -+ .ctrl2_reg = 0xb04, -+ .ctrl2_acquire_val = 0x303, -+ .ctrl2_release_val = 0x3, ++ .reset_reg = 0, ++ .reset_assert_val = 0x206, ++ .reset_status_bits = BIT(2), ++ .reset_deassert_val = 0x200, ++ .reset_release_val = 0x0, ++ .reset2_reg = 0xb04, ++ .reset2_acquire_val = 0x303, ++ .reset2_release_val = 0x3, +}; + -+static const struct of_device_id rzv2h_usb2phy_ctrl_match_table[] = { -+ { .compatible = "renesas,r9a09g057-usb2phy-ctrl", .data = &rzv2h_of_data }, ++static const struct of_device_id rzv2h_usb2phy_reset_of_match[] = { ++ { .compatible = "renesas,r9a09g057-usb2phy-reset", .data = &rzv2h_reset_of_data }, + { /* Sentinel */ } +}; -+MODULE_DEVICE_TABLE(of, rzv2h_usb2phy_ctrl_match_table); ++MODULE_DEVICE_TABLE(of, rzv2h_usb2phy_reset_of_match); + -+static struct platform_driver rzv2h_usb2phy_ctrl_driver = { ++static struct platform_driver rzv2h_usb2phy_reset_driver = { + .driver = { -+ .name = "rzv2h_usb2phy_ctrl", -+ .of_match_table = rzv2h_usb2phy_ctrl_match_table, ++ .name = "rzv2h_usb2phy_reset", ++ .of_match_table = rzv2h_usb2phy_reset_of_match, + }, -+ .probe = rzv2h_usb2phy_ctrl_probe, ++ .probe = rzv2h_usb2phy_reset_probe, +}; -+module_platform_driver(rzv2h_usb2phy_ctrl_driver); ++module_platform_driver(rzv2h_usb2phy_reset_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); -: ------------ > 3: e90a30abcf89 MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver Cheers, Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi All, This patch series adds support for the USB2PHY Port Reset control driver for the Renesas RZ/V2H(P) SoC. The changes include documenting the USB2PHY Port Reset control bindings and adding the driver. v2->v3 - Dropped Acks from Conor and Fabrizio, due to below changes - Renamed binding renesas,rzv2h-usb2phy-ctrl.yaml to renesas,rzv2h-usb2phy-reset.yaml - Renamed node name in example to reset-controller - Renamed function names in reset-rzv2h-usb2phy.c - Kept the reset line in asserted state during probe - Added comment for rzv2h_init_vals[] - Added entry in MAINTAINERS file v1->v2 - Dropped binding postfix in subject line for patch 1/2 - Moved acquiring the ctrl2 pin in deassert callback - Updated ctrl_status_bits Cheers, Prabhakar Lad Prabhakar (3): dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset driver reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P) MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver .../reset/renesas,rzv2h-usb2phy-reset.yaml | 56 ++++ MAINTAINERS | 8 + drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-rzv2h-usb2phy.c | 241 ++++++++++++++++++ 5 files changed, 313 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml create mode 100644 drivers/reset/reset-rzv2h-usb2phy.c