From patchwork Thu Nov 22 18:45:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10694709 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 352F417FE for ; Thu, 22 Nov 2018 18:45:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 21FA62CF01 for ; Thu, 22 Nov 2018 18:45:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 15EF12CEF9; Thu, 22 Nov 2018 18:45:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C9C22CEF9 for ; Thu, 22 Nov 2018 18:45:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729681AbeKWFZz (ORCPT ); Fri, 23 Nov 2018 00:25:55 -0500 Received: from mail-lf1-f67.google.com ([209.85.167.67]:45789 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729748AbeKWFZz (ORCPT ); Fri, 23 Nov 2018 00:25:55 -0500 Received: by mail-lf1-f67.google.com with SMTP id b20so7114724lfa.12 for ; Thu, 22 Nov 2018 10:45:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=subject:from:to:references:organization:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=lHRF8JiSotw7gOHMdQXBqjt0AcHczXZE9GdHmpsn0SI=; b=YLuo/Z2pjhVelarUAAAbL/9XxaS3N8WCZr5szOrfZa4OtvzlEz/0GAOM+3Qf+dhYBy +BfxF/jca7+fZyIZstqlFhvIcO0R99EVvQ2iOIg4iohbbnTNKCIBua74dp6AZ5C0L+mz aKMdv1cCAX6bRJ0e49tq4aW1Ax6EmkbN0+yfE/hEszjhIJrq+tWSDiMiImvffl8uNLZ/ itRs/EYg647njN0vnfsq/dmwAeoRVkvrC985BTSuiXm0XYM4oxShRfJtkgIIi3l+qWBp D9IUVY2K/ZRS5ixz88ip9fHYpO8uSaRn/dCLGTPh4eSUQ/Z7EA+8Lxl+xgoKsx+8YexI Xihg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=lHRF8JiSotw7gOHMdQXBqjt0AcHczXZE9GdHmpsn0SI=; b=nHU1NOQDFR/HUjg90f0CohAi92wkfO+6MeXNz82WZw+zvyNpUgr6ShkG8OwhBii7uR 0RceeCYplycmRyy4ijiKUi9+9HjlGZynv5sCneIR0yKp79xR0uOCI98gvDnpm7UiJFCx VRd59QqJk7FKWQIvhHpLbrM9UmQL4Hw+5ojquyP6T0jQbD1Dd9WGezvc62WyUp4Aid3N XyKbX6Ju8ds1qNtHkX3BOQ5mJ7wb7nQyM4dRhbOH+8usP1LkvD+1yidi1cEeUeMYNNLm YFFsVR78tJdcBUSI7Oxjy/JYyT6BrA2VUdWUs+rwFWWAEp/Umi/occzYICCRIBpPJyOl oJ5A== X-Gm-Message-State: AGRZ1gLTuwpWQNJ3IShFYupDslSnkzstKRgG1r0XWAoL74BYBCOo7JyP 1BUrXewrz3fgCQUxDg3cRauhMg== X-Google-Smtp-Source: AJdET5cY+/c5HL7+2OqELiCp/7fLLd9pZvHI8O84Y4feVn8q5UadoNB+T62kq/uho1OOCpU1UjFkng== X-Received: by 2002:a19:10da:: with SMTP id 87mr7107060lfq.60.1542912316114; Thu, 22 Nov 2018 10:45:16 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.85.10]) by smtp.gmail.com with ESMTPSA id d23sm7223882lfc.11.2018.11.22.10.45.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Nov 2018 10:45:15 -0800 (PST) Subject: [PATCH 4/4] clk: renesas: r8a77980-cpg-mssr: add RPC clocks From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: <0e51165d-65cb-1522-3174-b63818180070@cogentembedded.com> Date: Thu, 22 Nov 2018 21:45:14 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the RPCSRC internal clock on R-Car V3H (R8A77980) -- it's controlled by the RPCCKCR.DIV[4:3] on all the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field is different between SoCs. Add the RPC[D2] clocks (derived from this internal clock) and the RPC-IF module clock as well... Signed-off-by: Sergei Shtylyov --- drivers/clk/renesas/r8a77980-cpg-mssr.c | 40 +++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -10,6 +10,7 @@ * Copyright (C) 2015 Glider bvba */ +#include #include #include #include @@ -21,6 +22,10 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +enum r8a77980_clk_types { + CLK_TYPE_R8A77980_RPCSRC = CLK_TYPE_GEN3_SOC_BASE, +}; + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77980_CLK_OSC, @@ -41,12 +46,17 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_OCO, /* Module Clocks */ MOD_CLK_BASE }; +static const struct clk_div_table cpg_rpcsrc_div_table[] = { + { 2, 5 }, { 3, 6 }, { 0, 0 }, +}; + static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -65,8 +75,14 @@ static const struct cpg_core_clk r8a7798 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_R8A77980_RPCSRC, CLK_PLL1), DEF_RATE(".oco", CLK_OCO, 32768), + DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A77980_CLK_RPC), + /* Core Clock Outputs */ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), @@ -164,6 +180,7 @@ static const struct mssr_mod_clk r8a7798 DEF_MOD("gpio1", 911, R8A77980_CLK_CP), DEF_MOD("gpio0", 912, R8A77980_CLK_CP), DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), + DEF_MOD("rpc-if", 917, R8A77980_CLK_RPC), DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2), @@ -215,6 +232,27 @@ static int __init r8a77980_cpg_mssr_init return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } +static struct clk * __init r8a77980_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base, + struct raw_notifier_head *notifiers) +{ + if (core->type == CLK_TYPE_R8A77980_RPCSRC) { + const struct clk *parent = clks[core->parent]; + + if (IS_ERR(parent)) + return ERR_CAST(parent); + + return clk_register_divider_table(NULL, core->name, + __clk_get_name(parent), 0, + base + CPG_RPCCKCR, 3, 2, 0, + cpg_rpcsrc_div_table, NULL); + } else { + return rcar_gen3_cpg_clk_register(dev, core, info, clks, base, + notifiers); + } +} + const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a77980_core_clks, @@ -233,5 +271,5 @@ const struct cpg_mssr_info r8a77980_cpg_ /* Callbacks */ .init = r8a77980_cpg_mssr_init, - .cpg_clk_register = rcar_gen3_cpg_clk_register, + .cpg_clk_register = r8a77980_cpg_clk_register, };